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E1 Bit Errors are Caused by the Clock Problem in the MA5680T+OT925G Test

Publication Date:  2012-07-25 Views:  33 Downloads:  0
Issue Description
MA5680T version: V800R005C32B136
OT925G version: V100R002C01B023
In the MA5680T+OT925GE1 test, E1 bit errors occur continuously.
For the networking diagram and configurations, see the attachment. 
 
Alarm Information
Null
Handling Process
Relocate the tester and hang it beside the TOPA, set the clock of the tester to the internal clock, and loop back the E1 port on the OT925 by using a line. As a result, the clock of the whole E1 line is provided by the tester. Conduct the test again. Bit errors disappear and the E1 service becomes normal again. 
Root Cause
1. Check that the t-cont 1 bandwidth of the E1 service is 2752.
2. Check the configuration file and find that the clock source locks the topa port; however, there is a direct line loopback outside the topa port and no clock source is available. The E1 tester is hung below the OT925 and the clock is extracted from the line through From RX. Therefore, no clock is available on the whole line. 
 
Suggestions
When the E1 service is provided, it is recommended that a BIUA mother board with the CKMA subboard should be configured on the shelf. Then, the clock is precise to be a Stratum-3 clock. If this board is unavailable to extract the clock directly from the topa line, the clock is not precise enough to avoid clock slip. The impedance of the port should be configured to be consistent with that of the actual line. One channel of tcont bandwidth should be equal to 2,752 strictly, and two channels of tcont bandwidth should be equal to 2,752 ? 2. 

END