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FAQ-Clock Quality measurement and Analysis in V project

Publication Date:  2012-07-25 Views:  41 Downloads:  0
Issue Description
V project have many equipments of diffrerent producer including Huawei's RTN 910 & 950 and ECI MUX and Nokia MW and E/// Node B. E/// Node B can not got clock properly. clock connect solution as below.





Alarm Information
E/// Node B can not get clock properly, RNC unable made commission.



Handling Process
Through discuss with exprt of clock conclusion the ECI MUX was out of order. Therefor we gave below Test for find out the cause.

Following steps need to carry out to diagnose the clock quality issue:
a) Measure clock quality coming from the MUX E1 (2Mbps, 2G E1)
b) Check the clock quality when HW IDU is sync from 2Mhz MUX clock.
c) Also check the far end clock quality at HW IDU which will be used to give sync 2Mhz to NodeB (near end is in sync wit MUX 2Mhz clock)
d) Check the far end clock quality at PDH links output
f) Check the far end NodeB after rubidium source output 2Mhz to NodeB

Step a: Clock quality measurement was done at the MUX E1 (2Mbps, 2G E1), the clock quality is not good.

Step b: As there was a problem at MUX E1, We used 2Mhz clock from ECI MUX as there is no problem in Node B in near end. So we use the MUX 2Mhz. 910 track the 2Mhz. and then we test the IDU 2M bit/s .
Following is the test result: the output from the MUX 2Mhz is good. the measure value at 2Mbps HW IDU output is 0.19ppb (test time 15min.) this clock quality is good and the far end HW IDU will be in sync with this clock.(normally the output should less than 0.05ppm)

Step c.1 : At far end HW IDU is sync (step b) and 2Mhz output clock from HW IDU is tested. test time is 60min.test result is 0.65ppb
Following is the test result: the measure value at 2Mhz HW IDU output is 0.65ppb (test time 60min.)

Step c.2 : At far end HW IDU is sync (step b) and 2Mhz output clock from HW IDU is tested. This clock quality is good and within 50ppb. and there are ericsson engineer.
The measure value at 2Mhz HW IDU output is 0.42ppb (test time 15min.)

The measure value at 2Mhz HW IDU output is 0.62ppb (test time 180min.)

Step d.1: At far end we test the PDH links output 2M bit/s . Test time is 15min.test result is 0.26 ppb and there are Ericsson engineer.
Following is the test result: The measure value at QDH 2M bit/s is 0.26ppb (test time 15min.)

Step d.2: At far end we test the pdh links output 2M bit/s .
The measure value at PDH 2M bit/s is 0.49ppb (test time 180min.).

The measure value at PDH 2M bit/s is 0.51ppb (test time 180min.) and there are ericsson engineer.


Step f: At far end check the Node B after rubidium source output 2Mhz to NodeB

Result: NodeB is not up also.
1. We measured the clock quality at MUX E1 (2Mpbs, 2G E1), with the help of ANT 20 and RB clock source. The clock quality is not good. the 2G E1s coming from the MUX seems to be having problem related to the clock quality. This requires further investigation.

2. When we synchronize HW IDU with 2Mhz MUX clock in near end the value is 0.19ppb. in the far end the value are 0.65ppb 0.42ppb 0.62ppb after through our IDU. The clock quality in this EoPDH solution is good and within the required specification.

3. Even in this case NodeB is not sync, We need to analyze why the Node B is not sync even the clock quality is good. here we require vodafone team coordination to analyze the issue.

Required action items:

1. Test the clock quality of the other 2G E1s and see if the clock quality is good.
2. Provision new E1 or take a new MUX and test the clock quality.
3. And if the clock quality is ok, work with the Customer team to analyze why Node B is not in sync.




Root Cause
Screening analysis:

1、Check external clock source.
2、Check external clock source mode whether match with Huawei equipment.
3、Check SSM agreement mode.


 

Suggestions

1、External clock source 1 indicates the external clock source at the CLK1/TOD1 port on the CXPAR, CXPBR, CXPGR, or CXPHR board in physical slot 1. External clock source 2 indicates the external clock source at the CLK2/TOD2 port on the CXPAR, CXPBR, CXPGR, or CXPHR board in physical slot 2.
2、The internal clock source is always at the lowest priority and indicates that the NE works in the free-run mode.
3、The clock sources and the corresponding clock source priority levels are determined according to the clock synchronization schemes.

END