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VP8620 wrong system clock configuration causing error code

Publication Date:  2012-09-22 Views:  44 Downloads:  0
Issue Description
There is level 2 cascade connection MCU in system. MCU version is 2.13. Terminal version is 2.90. The terminal that has been set well and cascade connection MCU emerge CRC verify error code in port diagnose when having a conference. The error code rate is 10%. Only the MCU that hanging on the main MCU has no error. We can see large mosaic when watch other meeting place from this meeting place, and the sound is not good.  
Alarm Information
The error code rate is rather high in port diagnose, keeps on 10%.
Handling Process
1. First judgment is the problem should be on MCU and main meeting place, because the equipment was just set ready.
2. Check the equipment by self-loop, E16 self-loop normally. Loop back from transmission is normal too.
3. Exam system configuration, find that we set the clock to outer clock when we debug PRI. Now the PRI line disconnected, so we doubt is the wrong clock setting cause multi point line malfunction.
4. Change the clock to internal clock, reboot MCU host,and convene conference, most terminal and the connection of down level MCU and main MCU is back to normal. Error code disappeared.
Root Cause
When outer clock is set to line without signal or other down level equipment, the whole system clock emerge chaos, and has no unique correct clock source, causing majority line fracture receive data abnormally, and emerge verify error.
Suggestions
None

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