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Port change status from Up/Down because fault on the channel between the subcard and LPU

Publication Date:  2013-04-23 Views:  35 Downloads:  0
Issue Description
In logfile has appear messages about problem with board. Mar  6 2013 16:31:27+04:00 VLG_BNG_NE40_1 %%01SRM/2/NODERESUME(l)[7]:Slot=4;PIC1 of LPU 4: 1 Link Down of NP-3 PCS Status resumed.
Mar  6 2013 16:31:10+04:00 VLG_BNG_NE40_1 %%01PHY/4/PHY_STATUS_UP2DOWN(l)[8]:Slot=4;GigabitEthernet4/1/1 change status to down.
Mar  6 2013 16:31:10+04:00 VLG_BNG_NE40_1 %%01PHY/4/PHY_STATUS_UP(l)[9]:Slot=4;GigabitEthernet4/1/1 change status to up.
Mar  6 2013 16:31:10+04:00 VLG_BNG_NE40_1 %%01PHY/4/PHY_STATUS_UP2DOWN(l)[10]:Slot=4;GigabitEthernet4/1/1 change status to down.
Mar  6 2013 16:31:10+04:00 VLG_BNG_NE40_1 %%01PHY/4/PHY_STATUS_UP(l)[11]:Slot=4;GigabitEthernet4/1/1 change status to up.
Mar  6 2013 16:30:57+04:00 VLG_BNG_NE40_1 %%01SRM/2/NODEFAULT(l)[12]:Slot=4;PIC1 of LPU 4 is failed, perhaps 1 Link Down of NP-3 PCS Status is abnormal. (Reason="Port1 PCS link down")
Handling Process
Downloading logs and collect diagnostic information.
Root Cause
When the status or optical power of an interface changes, an incomplete packet is
transparently transmitted on the PHY chip, causing the interface connecting the PHY
chip to the MAC chip to go Down.
Solution
Must be installed patch V600R003SPH016. Such message caused by known problem. If an interface on the CR52EBGF or CR52EBGE subcard alternates between Up and Down or has low optical power, an alarm message "NP-3 PCS Status of PIC1 is abnormal" indicating a fault on the channel between the subcard and LPU is unexpectedly generated. As a result, the interface is physically Up but transmits no traffic. Condition: There is a possibility that the problem occurs if the following conditions are met: 1. A CR52EBGF or CR52EBGE subcard is installed on an LPUF-20/21. 2. An interface on the CR52EBGF or CR52EBGE subcard alternates between Up and Down or has low optical power. Root cause: When the status or optical power of an interface changes, an incomplete packet is transparently transmitted on the PHY chip, causing the interface connecting the PHY chip to the MAC chip to go Down.

END