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The Ethernet port which is down receives large numbers of pause frames

Publication Date:  2014-02-26 Views:  15 Downloads:  0
Issue Description

    One 10G port of CR52L2XXNB and other devices are directly connected by fiber,and flow downstream there. Abnormal power-down after the peer device. The locol port is down, but the port statistics continue to receive a lot of pause frames.As follows:

PIC0: version information
PCB         Version : CR52L2XXNB REV A


GigabitEthernet2/0/1 current state : DOWN
Line protocol current state : DOWN
-----------
The Vendor Name is FINISAR CORP.   , The Vendor PN is FTLX1412M3BCL
Transceiver max BW: 9900~11300Mbps, Transceiver Mode: Single Mode
WaveLength: 1310nm, Transmission Distance: 10km
Rx Optical Power: -37.06dBm, Tx Optical Power: -2.24dBm
Loopback:none, LAN full-duplex mode, Pause Flowcontrol:Receive Enable and Send Enable
Last physical up time   : 2014-02-11 07:54:22
Last physical down time : 2014-02-11 19:45:27
Statistics last cleared:2013-11-26 12:54:04
    Last 300 seconds input rate: 283389991 bits/sec, 553496 packets/sec
    Last 300 seconds output rate: 0 bits/sec, 0 packets/sec
    Input: 1517890929432933 bytes, 2148175167291 packets
    Output: 1430814631088691 bytes, 2330572390994 packets
    Input:
      Unicast: 1953705335789 packets, Multicast: 194469831500 packets
      Broadcast: 2 packets, JumboOctets: 138258268637 packets
      CRC: 0 packets, Symbol: 0 packets
      Overrun: 0 packets, InRangeLength: 0 packets
      LongPacket: 0 packets, Jabber: 0 packets, Alignment: 0 packets
      Fragment: 0 packets, Undersized Frame: 0 packets
     RxPause: 194454696418 packets

Handling Process
The pause frame statistic of CR52L2XXNB is got from MAC, MAC front FPGA.Afer check the registers of FPGA,  in the upstream entrance without any pause frame statistics , but exports there. So MAC pause frames generated by the FPGA.


Root Cause

When the peer device power-down,local port detected local fault signal.As described in IEEE802.3,when
this Local Fault status reaches an RS, the RS stops sending MAC data, and continuously generates a Remote
Fault status on the transmit data path. But the packet on data channel will still go to FPGA and cache on buffer. If lots of packets is put in the buffer and exceed High Water Mask, pasue frame will be sent.

Solution
 After interface up/down again, buffer is clear and pause frame stop.It will not affect service, just impact statistics.
Suggestions

Follow-up will be a patch optimization

END