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Logic device failure lead to peer end CRC wrong bag

Publication Date:  2014-12-25 Views:  36 Downloads:  0
Issue Description

One customer site of NE40E equipment, used the CR52L2XXNB subcard and wavelength division equipment interconnection. And this card 0 port interconnection wavelength division equipment receive about 3 % CRC packet, port 1 breakdown.

Handling Process

Live network cross - validation and found, fault point in CR52L2XXNB port subcard 0 The sending direction, and reset subcard fault is not restored. Then return laboratory for analysis.

1. loopback testing Confirm fault point:

Contains a PHY chip and a FPGA chip, and each layer can always be loopback, detailed - side inloop are as follows:

Through test equipment and 0 for port entries, doing external loopback subcard layers testing, ensure that passed through Which floor CRC error occurred package.

Finally, found in 1 and 2, 3 easy, and packet error free. Through the 4 places, began to appear CRC wrong bag. So that fault point is in the FPGA in MAC layer line.

2, locate the fault mode.

Of MAC layer get through message add CRC and distributed. Therefore initially suspected is MAC adds error CRC.

In testing seismographs captured through subcard four back the message, and packets, do comparison. The testing instrument is sent now add the CRC result is CCEE A6 04, but - back captured to Result shown in the following figure, into CCEC A6 04.

To sum up, FPGA MAC - add CRC unit comes up single bit faults, when CRC check result of this bit is set to 0,, breakdown. Is set to 1,, was changed to 0, lead to adds error CRC check results.

Root Cause
FPGA MAC layer in Single bit right lead to adds error CRC verification result.
Solution

Replace sub-card solution.

END