S5700(V200R003C00) 10GE port requires 10s to go Up

Publication Date:  2016-01-30 Views:  550 Downloads:  0
Issue Description
When plug-out and  immediately plug-in  optical connector at XGE port of S5710EI switch it can take about from 2sec to 10 sec for port return to UP state. Even when using carrier up-hold-time 0 command.

By default delay in reporting an interface Up event is 2000 milliseconds.

It takes much time to restore interface state.
Alarm Information
interface XGigabitEthernet1/0/1                                                                                                    

carrier up-hold-time 0                                                                                                            

#                                                                                                                                  

return

Oct  4 2015 11:26:43+08:00 S5710-123 %%01IFPDT/4/IF_STATE(l)[11]:Interface XGigabitEthernet1/0/1 has turned into DOWN state.

Oct  4 2015 11:26:47+08:00 S5710-123 %%01IFPDT/4/IF_STATE(l)[13]:Interface XGigabitEthernet1/0/1 has turned into UP state.

Oct  4 2015 11:31:18+08:00 S5710-123 %%01IFPDT/4/IF_STATE(l)[16]:Interface XGigabitEthernet1/0/1 has turned into DOWN state.

Oct  4 2015 11:31:23+08:00 S5710-123 %%01IFPDT/4/IF_STATE(l)[18]:Interface XGigabitEthernet1/0/1 has turned into UP state.

Oct  4 2015 11:32:29+08:00 S5710-123 %%01IFPDT/4/IF_STATE(l)[20]:Interface XGigabitEthernet1/0/1 has turned into DOWN state.

Oct  4 2015 11:32:39+08:00 S5710-123 %%01IFPDT/4/IF_STATE(l)[22]:Interface XGigabitEthernet1/0/1 has turned into UP state.

From logs we can see floating character of time difference between going DOWN and UP.

4 sec, 5 sec, 10 sec
Handling Process
The link state depend on the PHY state, include the state of PCS, PMA, PMD and XS layers. Any one of their state is fault will cause the error, and the link will not be UP, all layers states depend on the chip and the parameters setting.
Root Cause
When plug in and plug out the optical fibre cable, all layers states of PHY chip are fault, so the high layer software can’t identify the port state change, and then cause the port state change from DOWN to UP need long time.
Solution
Patch  V200R003SPH016 modifies parameters of PHY chip and reduces UP delay time to about 2 sec.

Bug "An error occurs when the 10GE interface is going Up" is fixed.

Applicable for:

S5700-SI, S5710-EI, S5700-HI, S5700-X-LI

END