Importing Time Signals from an External BITS Source
This section describes how to import time signals from an internal BITS source. On an SMPTE-2059-2 network, time signals are typically imported from an external building integrated timing supply system (BITS) source. Multiple routers can be configured to import time signals from an external BITS source before determining the master clock.
Context
A BITS source provides reference time signals. When dynamic BMC is used to select a clock source, multiple SMPTE-2059-2 devices can be configured to import BITS signals so that all these SMPTE-2059-2 devices participate in determination of the grandmaster clock. The grandmaster clock provides time signals for the entire SMPTE-2059-2 network, and other SMPTE-2059-2 devices use the SMPTE-2059-2 protocol to obtain clock synchronization information from the grandmaster clock. Perform the following steps on the routers connected to an external BITS source:
Perform the following steps on each router connected to an external BITS source on the SMPTE-2059-2 network:
Procedure
- Run system-view
The system view is displayed.
- Run clock bits-type [ chassis chassis-id ] { bits0 | bits1 | bits2 } 1pps input or clock bits-type [ chassis chassis-id ] { bits0 | bits1 } dcls
The type of the input time signals is specified.
Table 16-1 lists the types of signals that NE40E clock interfaces can receive.
Table 16-1 Types of signals that clock interfaces on NE40Es supportInterface Label on a Clock Board
Interface Label Set by Software
Interface Type
Type of Input or Output Signals
CLK/TOD0
BITS0
RJ45
Clock signals:2 Mbps clock signals
2 MHz clock signals
Time signals:1 PPS (RS422) + ASCII (RS422) time signals
Two direct current level shift (DCLS) clock channels (one channel for input, and the other channel for output)
CLK/TOD1
BITS1
RJ45
Clock signals:2 Mbps clock signals
2 MHz clock signals
Time signals:1 PPS (RS422) + ASCII (RS422) time signals
Two direct current level shift (DCLS) clock channels (one channel for input, and the other channel for output)
CLK/1PPS
BITS2
SMB
Clock signals:2 Mbps clock signals
2 MHz clock signals
Time signals:1 PPS (TTL) + ASCII (RS232) time signals
CLK/Serial
SMB
- Run ptp clock-source [ chassis chassis-id ] { bits0 | bits1 | bits2 } on [ slot slot-id ]
The device is configured to use BITS1 signals to select a clock source.
- (Optional) Run ptp clock-source [ chassis chassis-id ] { bits0 | bits1 | bits2 } { receive-delay receive-delay-value | send-delay send-delay-value } [ slot slot-id ]
The delay correction time for time signals on the BITS interface is set.
This command corrects the delay for the link between the BITS interface and the clock source or slave clock.
- Run commit
The configuration is committed.
