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MM910 Management Module V100R001 User Guide 24

This document provides the product description, installation and configuration methods, and common operations of the E9000 server chassis management module MM910.
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Huawei uses machine translation combined with human proofreading to translate this document to different languages in order to help you better understand the content of this document. Note: Even the most advanced machine translation cannot match the quality of professional translators. Huawei shall not bear any responsibility for translation accuracy and it is recommended that you refer to the English document (a link for which has been provided).
Hardware Structure

Hardware Structure

Figure 2-5 shows the components of the MM910.

Figure 2-5 MM910 hardware structure

1

CPU

2

CPLD

3

FPGA

4

LAN switch

5

Midplane power connector

6

Midplane signal connector 2

7

Midplane signal connector 3

8

Positioning pin

9

Midplane signal connector 1

-

-

Table 2-5 describes the components of the MM910.

Table 2-5 MM910 component

No.

Item

Description

1

CPU

A high-performance dual-core CPU is used.

The CPU is connected with five DDR3 dual in-line memory modules (DIMMs), including one used for error checking and correcting (ECC). Each DDR3 DIMM provides 0.25 GB capacity (1 GB capacity in total) and 667 MHz frequency.

2

CPLD

The MM910 requires many combination logic functions to operate properly. These functions are implemented by the complex programmable logical device (CPLD).

The CPLD performs the following functions:

  • Detects the installation status of each component in the chassis.
  • Provides a serial port to the midplane and implements serial port redirection.
  • Loads the field programmable gate array (FPGA) control module.
  • Controls switchovers between the active and standby MM910s.
  • Records component reset causes, for example, reset button pressed, watchdog overflow, and power-on.
  • Detects the clock.
  • Controls indicator states.
  • Queries component information.

3

FPGA

The FPGA performs the following functions:

  • Accesses the CPU local bus interface.
  • Provides eight independent I2C communication channels.
  • Decompresses video and caches data packets by using the peripheral DDR3 chip.
  • Provides one RS485 port on the panel.
  • Queries the power status of the chassis.

4

LAN switch

Provides the switching chip for 24 GE ports.

5

Midplane power connector

Allows the 12 V DC power to be supplied to the MM910.

6

Midplane signal connector 2

Provides signal ports between the MM910 and the midplane.

7

Midplane signal connector 3

8

Positioning pin

Ensures damage-free connections of signal connectors between the MM910 and the midplane.

9

Midplane signal connector 1

Provides a signal port between the MM910 and the midplane.

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Updated: 2019-04-10

Document ID: EDOC1000015900

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