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Huawei Server Brickland Platform BIOS Parameter Reference 23

This document describes the basic input/output system (BIOS) menu structure, parameters and common tasks based on the Brickland platform.
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Processor Configuration

Processor Configuration

This topic describes how to configure a processor on the Processor Configuration screen.

You can configure a processor on the Processor Configuration screen. Table 4-12 describes parameters on the screen.Figure 4-12, and Figure 4-13 show the Processor Configuration screen.

Figure 4-12 Processor Configuration screen 1

Figure 4-13 Processor Configuration screen 2

Table 4-12 Parameters on the Processor Configuration screen

Parameter

Description

Default Value

Processor Socket

Sequence number of a processor socket.

The display method of this parameter for the RH8100 V3 is as follows:

  • In single-system mode, Processor Socket is displayed as eight parameters: Socket 1 to Socket 8.
  • In dual-system mode, Processor Socket of system A is displayed as four parameters: Socket 1 to Socket 4.
  • In dual-system mode, Processor Socket of system B is displayed as four parameters: Socket 5 to Socket 8.

-

Processor ID

Processor ID.

-

Processor Frequency

Processor frequency.

-

Microcode Revision

Microcode version information of the CPU.

-

L1d Cache RAM

L1 data cache capacity.

-

L1i Cache RAM

L1 instruction cache capacity.

-

L2 Cache RAM

Level-2 cache capacity.

-

L3 Cache RAM

Level-3 cache capacity.

-

Processor 0 Version

Version information of processor 0.

The display method of this parameter for the RH8100 V3 are as follows:

  • In single-system mode, Processor x Version is displayed as eight parameters: Processor 1 Version to Processor 8 Version.
  • In dual-system mode, Processor x Version of system A is displayed as four parameters: Processor 1 Version to Processor 4 Version.
  • In dual-system mode, Processor x Version of system B is displayed as four parameters: Processor 5 Version to Processor 8 Version.

-

Processor 1 Version

Version information of processor 1.

-

Processor 2 Version

Version information of processor 2.

-

Processor 3 Version

Version information of processor 3.

-

Hyper-Threading [ALL]

Indicates whether to enable the hyper-threading function for Intel processors. If this function is enabled, each physical processor core functions as two logical processor cores. If this function is disabled, each physical processor core functions as only one logical processor core. Enabling this function increases the number of logical processor cores, improving system performance.

The options are as follows:

  • Enable
  • Disable

Enable

Monitor/Mwait

Specifies whether to enable MONITOR/MWAIT instructions. After MONITOR/MWAIT instructions are enabled, the CPU status can be monitored, which optimizes the execution of CPU instructions. If Enabled is selected, some OSs will acquire the capability of automatically adjusting energy-saving options. Therefore, if you want to disable energy-saving options, you must also disable this parameter.

The options are as follows:

  • Enable
  • Disable

Disable

Execute Disable Bit

EDB (Execute Disable Bit) is an Intel hardware-based security function that helps reduce system viruses and malicious code. When a malicious worm attempts to insert code into the buffer, the processor disables code execution to prevent damage and worm propagation. To use EDB, the OS must also support this function. Some OSs (including Windows Server 2012 and Windows Server 2012 R2) support EDB.

The options are as follows:

  • Enable
  • Disable

Enable

VT-x

Indicates whether to enable the CPU virtualization technology. Virtualization layers or OSs that support this parameter can use hardware capabilities of Intel virtualization technology. The Intel virtualization technology needs to be enabled at some virtualization layers. When virtualization layers or OSs that support this function are not used, you can also enable this function.

The options are as follows:

  • Enable
  • Disable

Enable

Hardware Prefetcher

Indicates whether to enable the hardware prefetcher feature. Before processing instructions or data, the CPU prefetches these instructions or data and saves them to level-2 cache. This reduces memory read time, eliminates potential bottlenecks, and therefore improves system performance. In sequential memory access, this function can accelerate data access. In random memory access, you are advised to disable this function.

The options are as follows:

  • Enable
  • Disable

Enable

Adjacent Cache Prefetch

Indicates whether to enable the adjacent cache prefetcher function. After this function is enabled, when the computer reads data, it prefetches data adjacent to the data. This improves read speed significantly.

The options are as follows:

  • Enable
  • Disable

Enable

DCU Streamer Prefetcher

Indicates whether to enable the DCU streamer prefetcher function. This function is enabled by default and may have impact on performance depending on applications that run on the server. This function allows CPU data to be prefetched and therefore reduces data read time.

The options are as follows:

  • Enable
  • Disable

Enable

DCU IP Prefetcher

Indicates whether to enable the DCU IP prefetcher function. This function enables the system to check historical records for the data that must be prefetched. This function is enabled by default and may have impact on performance depending on applications that run on the server, and therefore reduces data read time.

The options are as follows:

  • Enable
  • Disable

Enable

DCU Mode

DCU mode, which is used to enable the error correcting function of level-1 cache.

The options are as follows:

  • 32KB 8Way Without ECC
  • 16KB 4Way With ECC

32KB 8Way Without ECC

X2APIC

Indicates whether to enable the extended Advanced Programmable Interrupt Controller (APIC). x2APIC is an interruption information transmission mechanism of Intel processors, generally used in virtualization scenarios. x2APIC support allows an OS to efficiently run on a server with multiple CPU cores and optimizes interruption distribution in virtualization environments. x2APIC support is enabled in most cases. If x2APIC support is enabled, the ACPI x2APIC control structure is generated, and the x2APIC option is displayed during OS loading. Enabling this function is not equal to enabling the x2APIC hardware, but providing the OS with necessary x2APIC support. However, some virtualization layers or OSs of early versions may not support x2APIC. You need to disable x2APIC support for them.

The options are as follows:

  • Enable
  • Disable

Disable

AES-NI

Indicates whether to enable a CPU to support the Intel Advanced Encryption Standard (AES) New Instructions (AES-NI). The AES-NI is primarily used in a virtualized system. If the CPU supports the AES-NI, the system performance will be improved.

The options are as follows:

  • Enable
  • Disable

Enable

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Updated: 2018-12-03

Document ID: EDOC1000039573

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