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Huawei Server Brickland Platform BIOS Parameter Reference 23

This document describes the basic input/output system (BIOS) menu structure, parameters and common tasks based on the Brickland platform.
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Memory RAS Configuration

Memory RAS Configuration

This topic describes how to configure a memory module on the Memory RAS Configuration screen.

On the Memory RAS Configuration screen, you can configure a memory module, including enabling the memory module, setting a mask, and configuring interleaved memory.

Table 5-24 describes the parameters on the Memory RAS Configuration screen.Figure 5-27 shows the screen.

Figure 5-27 Memory RAS Configuration screen
Table 5-24 Parameters on the Memory RAS Configuration screen

Parameter

Description

Default Value

Memory Thermal Throttling

Indicates whether to enable the temperature control function of the memory. The options are as follows:

  • Enable
  • Disable

Enable

NUMA

Indicates whether to enable the NUMA configuration menu. The options are as follows:

  • ON (1-way)
  • ON (2-way)
  • OFF (4-Way)
  • OFF (8-Way)

1-way indicates one-way interleaving, that is, memory interleaving in the same memory controller, 2-way indicates two-way interleaving, and the others follow the same rule. The more interleaving ways, the higher memory bandwidth, but the access efficiency may be lower.

ON (2-way)

Memory Migration

Indicates whether to enable the memory migration function. The options are as follows:

  • Enable
  • Disable
NOTE:

If Memory Migration is enabled, the Migration Spare MC0 and Migration Spare MC1 parameters are displayed. However, the specific parameters displayed vary depending on the server model:

  • For an RH5885H V3 server, Spare Riser1 to Spare Riser8 are displayed under Migration Spare.
  • For an RH8100 V3 server:
  • Single-system mode: Board 1 to Board 16 are displayed under Migration Spare.
  • Dual-system mode: Board 1 to Board 8 are displayed under Migration Spare for system A, and Board 9 to Board 16 are displayed for system B.

Disable

Device Tagging

Indicates whether to enable the SDDC function. The memory ECC mechanism can only correct single-bit errors and detect multi-bit errors, that is, single-error correction, double error detection (SEC-DED). In practice, the failure of a single memory chip usually results in errors of all bits output by the chip. The SDDC mechanism can correct multi-bit errors in a single memory chip (common x4- or x8-chip DDR DIMM with ECC). To enable SDDC for an x8-chip DIMM, configure the lockstep mode for the DIMM first. The options are as follows:

  • Enable
  • Disable

Enable

DDDC Support

Indicates whether to enable the DDDC function. (When DDDC Support is in gray, the function is disabled.) DDDC supports only x4-chip DIMMs in lockstep mode. Memory chip replacement can be performed twice when a DIMM error occurs. The options are as follows:

  • Rank DDDC
  • Bank DDDC
  • Disable
NOTE:

If DDDC Support is set to Rank DDDC or Bank DDDC, DDDC Wirekill and DDDC Wirekill Threshold are displayed.

Disable

Memory Rank Sparing

Indicates whether to enable the memory rank sparing function. (When Memory Rank Sparing is in gray, the function is disabled.) In the Rank Sparing mode, one rank is used as the standby rank for other ranks in the same channel. The standby rank is reserved and does not serve as the system memory. The memory of the standby rank must be greater than or equal to that of all other ranks in the same channel. After memory rank sparing is enabled, the memory of the standby rank is not included in the calculation of the total available capacity. The options are as follows:

  • Enable
  • Disable
NOTE:

If the Memory Rank Sparing is enabled, the following parameters are displayed:

  • For the RH8100 V3:
  • In single-system mode: Socket 0 Branch 0 Spare to Socket 7 Branch 1 Spare
  • System A in dual-system mode: Socket 0 Branch 0 Spare to Socket 3 Branch 1 Spare
  • System B in dual-system mode: Socket 4 Branch 0 Spare to Socket 7 Branch 1 Spare
  • For other servers: Socket 0 Branch 0 Spare to Socket 3 Branch 1 Spare

Disable

Spare Error/Memory Correctable Threshold

Indicates the spare error threshold.

6000

Memory Mirroring

Indicates whether to enable memory mirroring. (When Memory Mirroring is in gray, the function is disabled.) The options are as follows:

  • Full CH Mirroring: indicates channel memory mirroring.
  • Partial CH Mirroring: indicates 64 MB memory mirroring.
  • Disable: disables memory mirroring.
NOTE:

The Memory Mirroring parameter is unavailable for Haswell and available for Broadwell.

If Memory Mirroring is set to Full CH Mirroring, the following parameters are displayed:

  • For the RH8100 V3:
  • In single-system mode: Memory Mirroring SCK0 MC0 to Memory Mirroring SCK7 MC1
  • System A in dual-system mode: Memory Mirroring SCK0 MC0 to Memory Mirroring SCK3 MC1
  • System B in dual-system mode: Memory Mirroring SCK4 MC0 to Memory Mirroring SCK7 MC1
  • For other servers: Memory Mirroring SCK0 MC0 to Memory Mirroring SCK3 MC1

If Memory Mirroring is set to Partial CH Mirroring, the following parameters are displayed:

  • For the RH8100 V3:
  • In single-system mode: Partial Mirroring SCK0 MC0 to Partial Mirroring SCK7 MC1
  • System A in dual-system mode: Partial Mirroring SCK0 MC0 to Partial Mirroring SCK3 MC1
  • System B in dual-system mode: Partial Mirroring SCK4 MC0 to Partial Mirroring SCK7 MC1
  • For other servers: Partial Mirroring SCK0 MC0 to Partial Mirroring SCK3 MC1

Disable

SB Persistent error

Indicates whether to enable the function for detecting southbridge (SB) errors on the SMI2 channel. The options are as follows:

  • Enable
  • Disable

Enable

SB Error Threshold

Indicates the threshold for SB errors on the SMI2 channel.

10

Link Fail Threshold

Indicates the lane failover threshold on the SMI2 channel.

7

Refresh Options

Indicates the self-refresh mode. The memory controller updates memory data periodically. The normal refresh rate is 1x. If the running temperature of the memory module exceeds the upper threshold or you want to improve system reliability, you can set the refresh rate to 2x. The options are as follows:

  • Acc Self Refr: memory self-refresh.
  • F2x Refresh: 2x memory self-refresh.
  • Force 2x Refresh:force 2x memory self-refresh.

Force 2x Refresh

DDDC Wirekill

Indicates whether to enable the wire correction function. The options are as follows:

  • Enable
  • Disable

Disable

DDDC Wirekill Threshold

Indicates the wire correction threshold.

3

Socket 0 Branch 0 Spare

Indicates whether to enable the spare function for a DIMM in branch 0 of CPU 0. The options are as follows:

  • Enable
  • Disable
NOTE:
  • The parameters Socket 0 Branch 1 Spare to Socket 7 Branch 1 Spare have similar meanings to Socket 0 Branch 0 Spare.
  • If Socket X Branch Y Spare is set to Enable, SKTX MCY CH0 Spare Rank Count, SKTX MCY CH1 Spare Rank Count, SKTX MCY CH2 Spare Rank Count and SKTX MCY CH3 Spare Rank Count are displayed.

Disable

SKTX MCY CH0 Spare Rank Count

Indicates the number of spare ranks for channel 0 of branch Y of CPU X. The options are as follows:

  • Auto
  • 1
  • 2
  • 3
  • 4
  • Disable

Auto

SKTX MCY CH1 Spare Rank Count

Indicates the number of spare ranks for channel 1 of branch Y of CPU X. The options are as follows:

  • Auto
  • 1
  • 2
  • 3
  • 4
  • Disable

Auto

SKTX MCY CH2 Spare Rank Count

Indicates the number of spare ranks for channel 2 of branch Y of CPU X. The options are as follows:

  • Auto
  • 1
  • 2
  • 3
  • 4
  • Disable

Auto

SKTX MCY CH3 Spare Rank Count

Indicates the number of spare ranks for channel 3 of branch Y of CPU X. The options are as follows:

  • Auto
  • 1
  • 2
  • 3
  • 4
  • Disable

Auto

Memory Mirroring SCK0 MC0

Indicates whether to enable the SCK0 MC0 Mirror mode. The options are as follows:

  • Enable
  • Disable

The parameters Memory Mirroring SCK0 MC1 to Memory Mirroring SCK7 MC1 have similar meanings to Memory Mirroring SCK0 MC0.

Disable

Partial Mirroring SCK0 MC0

Indicates the partial mirroring memory capacity for SCK0 MC0.

The parameters Partial Mirroring SCK0 MC1 to Partial Mirroring SCK7 MC1 have similar meanings to Partial Mirroring SCK0 MC0.

1 (64 MB)

NB Error Threshold

Indicates the threshold for NB errors on the SMI2 channel.

255

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Updated: 2018-12-03

Document ID: EDOC1000039573

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