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Huawei Server Maintenance Manual 09

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Locate the Slot of a Faulty DIMM by Using the MISC Register Value in the FDM Logs

Locate the Slot of a Faulty DIMM by Using the MISC Register Value in the FDM Logs

Problem Description

Table 5-257 Basic information



Source of the Problem

KunLun 9016

Intended Product

KunLun 9008/9016/9032

Release Date



DIMM slot


On a KunLun 9000 series server, an error is generated in the FDM logs during memory inspection. However, the slot of the faulty DIMM is not provided.

Key Process and Cause Analysis

When this problem occurs, use the CPU slot number, DIMM channel number and MISC register to locate the slot of the faulty DIMM.

The FDM error record in the preceding figure shows that the CPU socket of the faulty DIMM is CPU3 (the third physical CPU), the channel is IMC 0 CH3 (the last channel of the first memory board on the CPU board). Each CPU has two IMCs, IMC 0 corresponds to the first memory board, and IMC 1 corresponds to the second memory board.

The memory channels on an IMC are described as follows:

J01 to J03: Channel 0

J04 to J06: Channel 1

J07 to J09: Channel 2

J10 to J12: Channel 3

  1. DIMM channel:

    Use bits 50 to 46 in the MISC register to locate faulty rank of the channel.

  2. MISC register:

    The FDM log displayed in Figure 1 is used as an example. The decimal value of bits 50 to 46 in the MISC register is 7, indicating that the faulty rank is rank 7.

  3. Register parsing:

    The mapping between the ranks and DIMM positions is as follows:


    Ranks 0 to 3: DIMM1

    Ranks 4 to 5: DIMM2

    Ranks 6 to 7: DIMM3


    Ranks 0 to 3: DIMM1

    Ranks 4 to 7: DIMM2

    In this case, all 12 DIMMs are inserted. Therefore, the DIMM configuration is 3DPC. The DIMM corresponding to rank 7 is DIMM3. Use the \one_touch_info_all\summaryinfo.txt file of the KunLun server to locate the DIMM slot.

  4. Faulty DIMM position:

    Based the CPU socket number, memory board slot number, and DIMM channel number, the faulty DIMM is in the J12 slot on the first memory board of the third CPU.

Conclusion and Solution




Updated: 2019-02-25

Document ID: EDOC1000041338

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