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S12700 Series Agile Switches Hardware Description

This document describes hardware components of the S12700, including the cabinet, chassis, power supply facilities, fan modules, cards, cables, and pluggable modules for interfaces. You can find useful information about S12700 hardware components from this document.
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LE0D00CKMA00 Clock Pinch Board,-1588

LE0D00CKMA00 Clock Pinch Board,-1588

Version Mapping

Table 7-64 Switch chassis and software versions matching the CKM daughter card

Card Name

S12700 Chassis


Supported in V200R010C00 and later versions


The LE0D00CKMA00 is a daughter card installed in the main control unit of the S12700 to provide clock and time synchronization. This card has two Building Integrated Timing Supply (BITS) ports.

The LE0D00CKMA00 can be installed in the ET1D2MPUA000, ET1D2MPUBC01, and ET1D2MPUBC00.

Figure 7-33 Appearance of the LE0D00CKMA00


The LE0D00CKMA00 consists of the following functional units:

  • Clock synchronization unit (synchronous Ethernet clock)
  • Time synchronization unit (IEEE 1588 module)

The LE0D00CKMA00 provides the following functions:

  • Provides the 19.44 MHz system clock and external clock signals. The output clock signal complies with the ITU-T G.813 standard.
  • Implements the IEEE 1588 protocol to ensure time synchronization on the network. Time synchronization accuracy is within 0.1 us, which complies with the 1588v2 protocol.

Usage Constraints

If the switch is equipped with two MPUs, you must install clock daughter cards on both the active and standby MPUs.

Components and Ports

Figure 7-34 Components on the LE0D00CKMA00

Table 7-65 Components on the LE0D00CKMA00






The studs fix the clock daughter card on the MPU.


Double-edge connector

The clock daughter card uses these connectors to exchange signals with the MPU.

The LE0D00CKMA00 has two BITS ports, which are presented by CLK1 and CLK2 on the MPU, as shown in Figure 7-35.

Figure 7-35 BITS ports of the LE0D00CKMA00 on the MPU panel

Table 7-66 Ports on the LE0D00CKMA00


Port on the MPU Panel

Port on the LE0D00CKMA00





A BITS port can be configured as an input or output port.

  • Input port: receives 2.048 MHz clock signals, 2.048 Mbit/s clock signals, 1.544 Mbit/s clock signals, 1 pulse per second (pps) clock signals, or DC level shift (DCLS) code streams from the upstream device and generates 19.44 MHz clock signals for the system. The BITS port also obtains time information and provides time information for LPUs.
  • Output port: sends 2.048 MHz clock signals, 2.048 Mbit/s clock signals, 1.544 Mbit/s clock signals, 1 pps clock signals, or DCLS code streams to the downstream device.




BITS port
Table 7-67 BITS port attributes
Attribute Description
Connector type RJ45
Working mode

Transmission rate

  • Clock synchronization: 2 MHz, 2 Mbps, 1.544 Mbps
  • Time synchronization: 9600 bit/s (full-duplex mode supported)
Standards compliance

Clock synchronization: E1 and T1

Time synchronization: DCLS and time of day (ToD)


Table 7-68 Specifications of the LE0D00CKMA00



Physical specifications

  • Dimensions (H x W x D): 2.0 mm x 100.0 mm x 145.0 mm (0.08 in. x 3.94 in. x 5.71 in.)
  • Weight: 0.10 kg (0.2 lb)
  • Maximum power consumption: 6 W

Environment specifications

  • Operating temperature: 0°C to 45°C (32°F to 113°F)
  • Operating relative humidity: 5% RH to 95% RH (noncondensing)
  • Storage temperature: -40°C to +70°C (-40°F to +158°F)
  • Storage relative humidity: 5% RH to 95% RH (noncondensing)

Ordering Information

Card ordering information is subject to updates with product version upgrades. The ordering information provided in this manual is for reference only. To obtain the latest ordering information, contact Huawei switch distributors or Huawei local office.

Table 7-69 Ordering information
Part Number Card Description Card Model
03020PPT Clock Pinch Board LE0D00CKMA00
Updated: 2019-08-19

Document ID: EDOC1000047496

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