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ES3000 V3 NVMe PCIe SSD User Guide 20

This document provides the product information about the Huawei ES3000 V3 PCIe SSD (ES3000 V3 for short) and describes how to install, configure, operate, and maintain the ES3000 V3.
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Huawei uses machine translation combined with human proofreading to translate this document to different languages in order to help you better understand the content of this document. Note: Even the most advanced machine translation cannot match the quality of professional translators. Huawei shall not bear any responsibility for translation accuracy and it is recommended that you refer to the English document (a link for which has been provided).
NVMe Basic Management Command

NVMe Basic Management Command

The I2C address of NVMe out-of-band management commands is 0x6A (excluding the R/W bits).

Table B-1  NVMe basic management data structure
Command Code Offset (Byte) Description
0 00 Length of Status: Indicates number of additional bytes to read before encountering PEC. This value should always be 6 (06h) in implementations of this version of the spec.
01

Status Flags(SFLGS): This field indicates the status of the NVM subsystem.

SMBus Arbitration: Bit 7 is set '1' after a SMBus block read is completed all the way to the stop bit without bus contention and cleared to '0' if a SMBus Send Byte FFh is received on this SMBus slave address.

Drive Not Ready: Bit 6 is set to '1' when the subsystem cannot process NVMe management commands, and the rest of the transmission may be invalid. If cleared to '0', then the NVM subsystem is fully powered and ready to respond to management commands. This logic level intentionally identifies and prioritizes powered up and ready drives over their powered off neighbors on the same SMBus segment.

Drive Functional: Bit 5 is set to '1' to indicate an NVM subsystem is functional. If cleared to '0', then there is an unrecoverable failure in the NVM subsystem and the rest of the transmission may be invalid.

Reset Not Required: Bit 4 is set to '1' to indicate the NVM subsystem does not need a reset to resume normal operation. If cleared to '0' then the NVM subsystem has experienced an error that prevents continued normal operation. A controller reset is required to resume normal operation.

Port 0 PCIe Link Active: Bit 3 is set to '1' to indicate the first port's PCIe link is up (i.e., the Data Link Control and Management State Machine is in the DL_Active state). If cleared to '0', then the PCIe link is down.

Port 1 PCIe Link Active: Bit 2 is set to '1' to indicate the second port's PCIe link is up. If cleared to '0', then the second port's PCIe link is down or not present.

Bits 1 and 0 must be set to 1.

02 SMART Warnings: This field shall contain the Critical Warning field (byte 0) of the NVMe SMART / Health Information log. Each bit in this field shall be inverted from the NVMe definition (i.e., the management interface shall indicate a '0' value while the corresponding bit is '1' in the log page). Refer to the NVMe specification for bit definitions.
If there are multiple controllers in the NVM subsystem, the management endpoint shall combine the Critical Warning field from every controller such that a bit in this field is:
  • Cleared to '0' if any controller in the subsystem indicates a critical warning for that corresponding bit.
  • Set to '1' if all controllers in the NVM subsystem do not indicate a critical warning for the corresponding bit.
03 Composite Temperature(CTemp): This field indicates the current temperature in degrees Celsius. If a temperature value is reported, it should be the same temperature as the Composite Temperature from the SMART log of hottest controller in the NVM subsystem. The reported temperature range is vendor specific, and shall not exceed the range -60 to +127°C.
Value Detailed Description
00h-7Eh Temperature is measured in degrees Celsius (0 to 126C)
7Fh 127C or higher
80h No temperature data or temperature data is more the 5 seconds old.
81h Temperature sensor failure
82h-C3h Reserved
C4 The temperature is –60°C or lower.
C5-FFh Temperature measured in degrees Celsius is represented in twos complement (-1 to -59C)
04 Percentage Drive Life Used(PDLU): Contains a vendor specific estimate of the percentage of NVM subsystem NVM life used based on the actual usage and the manufacturer's prediction of NVM life. A value of 100 indicates that the estimated endurance of the NVM in the NVM subsystem has been consumed, but may not indicate an NVM subsystem failure. The value can be greater than 100. The value is always set to 255 if it is greater than 254.
06:05 Reserved
07 PEC: An 8 bit CRC calculated over the slave address, command code, second slave address and returned data. Algorithm is in SMBus Specifications.
8 08 Length of identification: Indicates number of additional bytes to read before encountering PEC. This value should always be 22 (16h) in implementations of this version of the spec.
10:09 Vendor ID: The 2 byte vendor ID, assigned by the PCI SIG. Should match VID in the Identify Controller command response. MSB is transmitted first.
30:11 Serial Number: 20 characters that match the serial number in the NVMe Identify Controller command response. First character is transmitted first.
31 PEC: An 8 bit CRC calculated over the slave address, command code, second slave address and returned data. Algorithm is in SMBus Specifications.
32 255:32 Vendor Specific: Vendor specific data.
Table B-2  Vendor-specific data structure
Command Code Offset (Byte) Description
32 32 Data byte length defined by the vendor before PEC. This domain must be set to 22(16h).
33 Reserved byte. The default value is 0.
34 Current power consumption. Unit: W
35 Reserved byte. The default value is 0x80.
36 Reserved byte. The default value is 0.
37 Reserved byte. The default value is 0.
38 Reserved byte. The default value is 0.
46:39 Firmware Version: 8-byte firmware version number in ASCII code.
54:47 Bootloader Version: 8-byte bootloader version number in ASCII code.
55 PEC: An 8 bit CRC calculated over the slave address, command code, second slave address and returned data. Algorithm is in SMBus Specifications.
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Updated: 2019-03-12

Document ID: EDOC1000101091

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