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PCIe Topology and Relationships
See the following figure for the topological relationships among slave physical CPUs of front and rear I/O external card slots of the RH8100:
Using an example of installing two 10GE NICs, A and B, respectively, in slot 3 and slot 8 of the rear I/O board, because the physical CPUs to which such NICs are subordinated are CM (CPU Module)-slot6 and CM-slot3, the relationships between CPU nodes and physical CPU sockets of the RH8100 are as follows:
Physical CPU Nodes |
Logic CPU Nodes |
|---|---|
1 |
0 |
2 |
3 |
3 |
1 |
4 |
2 |
5 |
7 |
6 |
6 |
7 |
4 |
8 |
5 |
Namely, the logic CPU nodes of A and B are node6 and node1 respectively. During the bonding, the interrupt request (IRQ) ID of A shall be bonded on the CPU thread subordinate to node6, and the IRQ ID of B on the CPU thread subordinate to node1.
