No relevant resource is found in the selected language.

This site uses cookies. By continuing to browse the site you are agreeing to our use of cookies. Read our privacy policy>Search

Reminder

To have a better experience, please upgrade your IE browser.

upgrade

Log Reference

S9300, S9300E, and S9300X V200R010C00

This document provides the explanations, causes, and recommended actions of logs on the product.
Rate and give feedback:
Huawei uses machine translation combined with human proofreading to translate this document to different languages in order to help you better understand the content of this document. Note: Even the most advanced machine translation cannot match the quality of professional translators. Huawei shall not bear any responsibility for translation accuracy and it is recommended that you refer to the English document (a link for which has been provided).
CLOCK/4/DCLS_LOS

CLOCK/4/DCLS_LOS

Message

CLOCK/4/DCLS_LOS:The BITS[ULONG] DCLS signal is lost.

Description

The BITS input DCLS signal is lost.

Parameters

Parameter Name Parameter Meaning
[ULONG] Indicates the number of the BITS interface. The values are as follows:

0: BITS0 interface

1: BITS1 interface

Possible Causes

1. The device where the BITS interface resides is faulty.

2. The cable connection between the BITS interface and the local device is abnormal.

Procedure

  • Check whether the BITS interface is working normally by running the display clock self-test-result command to check whether the status of components including the E1/T1 framer and FPGA is normal.
  • Check whether the link is normal.
  • Check whether the BITS interface sends DCLS signal.
  • Contact technical support personnel.
Translation
Download
Updated: 2019-08-21

Document ID: EDOC1000142069

Views: 569406

Downloads: 37

Average rating:
This Document Applies to these Products
Related Version
Related Documents
Share
Previous Next