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Log Reference

S9300, S9300E, and S9300X V200R010C00

This document provides the explanations, causes, and recommended actions of logs on the product.
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CLOCK/4/TS_ABNORMAL:The timestamp is abnormal. (MaxPD1588=[LONG], MinPD1588=[LONG])


Transient occurs in the time stamp received from the upstream device. The maximum phase discrimination is greater than 30 or the minimum phase discrimination is smaller than -30. The log records the maximum phase discrimination and the minimum phase discrimination.


Parameter Name Parameter Meaning


Indicates the maximum value of phase discrimination.


Indicates the minimum value of phase discrimination.

Possible Causes

1. Generally, jitter occurs during the switchover of clock source. This log is generated when the jitter occurs.

2. The performance of the traced clock source degrades, for example, the time jitter occurs.


  • If the clock source is switched, this is a normal situation.
  • If the clock source of the upstream device is switched, this is a normal situation.
  • After the clock source is switched, if the log is generated on all the interfaces of the local device, the clock board of the local device may be faulty. Then perform an active/standby switchover. If the log does not occur, the original active clock board is faulty. You can replace the clock board.
  • Record this log message and contact technical support personnel.
Updated: 2019-08-21

Document ID: EDOC1000142069

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