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Log Reference

S9300, S9300E, and S9300X V200R010C00

This document provides the explanations, causes, and recommended actions of logs on the product.
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CLOCK/4/BITS_SW_FR_IVLD

CLOCK/4/BITS_SW_FR_IVLD

Message

CLOCK/4/BITS_SW_FR_IVLD:BITS[ULONG] switches from the invalid source to [STRING].

Description

The BITS clock source is selected for the first time.

Parameters

Parameter Name Parameter Meaning

[ULONG]

Indicates the number of BITS output interface. The values are as follows:
  • 0: Indicates that the source clock signal is output from BITS0.
  • 1: indicates that the source clock signal is output from BITS1.

[STRING]

Indicates the type of the clock source. The values are as follows:
  • 0) Inner Clock: internal clock.
  • 1) BITS0: BITS0 clock.
  • 2) BITS1: BITS1 clock.
  • 3) Peer Board BITS0: BITS0 clock on the peer board.
  • 4) Peer Board BITS1: BITS1 clock on the peer board.
  • 5) Left Frame Clock: clock of the left frame.
  • 6) Right Frame Clock: clock of the right frame.
  • 7) FSU: flexible service unit.
  • 8) Peer Board FSU: flexible service unit of the peer board.
  • 9) System Clock: system clock.
  • 10) Peer System Clock: system clock of the peer board.

Possible Causes

The BITS clock source is selected for the first time.

Procedure

  • This log message is informational and no action is required.
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Updated: 2019-08-21

Document ID: EDOC1000142069

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