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S12700 V200R010C00 Configuration Guide - Device Management

This document describes the principles and configurations of the Device Management features, and provides configuration examples of these features.
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Huawei uses machine translation combined with human proofreading to translate this document to different languages in order to help you better understand the content of this document. Note: Even the most advanced machine translation cannot match the quality of professional translators. Huawei shall not bear any responsibility for translation accuracy and it is recommended that you refer to the English document (a link for which has been provided).
Principles

Principles

In Ethernet clock synchronization, clock signals are transmitted at the physical layer. A device requires a clock module (a clock pinch board) to send high-accuracy system clock signals to all Ethernet interface line cards, as shown in Figure 6-1.

Figure 6-1  Clock frequency synchronization

In the receiving direction, the PHY chip of an Ethernet interface line card restores and abstracts clock signals sent from the circuit, divides the frequency, and sends the clock signals to the clock pinch board. The clock pinch board selects the clock with the highest accuracy as the reference clock source according to the SSM protocol and other related information, and then sends the clock source system phase-locked loop (PLL). The PLL traces this reference clock source and sends high-accuracy clock signals to each interface line card.

In the sending direction, the PLL on an Ethernet interface line card traces the clock source sent from the clock pinch board and generates the reference clock for data transmission of the PHY chip.

Through this process, clock frequency signals can be transmitted at the physical layer. The SSM quality level of the Ethernet clock is transmitted through dedicated SSM frames.

On the device, clock signals are transmitted as follows:

  1. Clock signals from different clock sources are sent to the clock pinch board.

    The clock pinch board of the device can obtain clock signals from the following components:
    • Circuit clock

      The switching chip on the LPU of the device can obtain clock signals from an optical interface, and then sends the clock signals to the clock pinch board on the main control board through the circuit on the backplane.

    • External clocks, such as the building integrated timing supply (BITS) clocks
    • High-accuracy oscillator of the clock pinch board, which is used in emergencies when LPUs and external clocks cannot provide the clock source
  2. The clock pinch board selects the best clock source from received clock signals, and then sends 19.44 MHz clock signals to all LPUs through downlink circuits on the backplane.

  3. The switching chip of each LPU uses this clock signal as the drive clock signal to send and receive packets.

Synchronization Status Message

The synchronization status message (SSM) is used to transmit the quality level of timing signals on the synchronization timing link. A node on the Synchronous Digital Hierarchy (SDH) network or clock synchronization network can obtain the clock information of the upstream device by parsing the SSM message. The node performs operations such as tracing, switching, or holding the local clock source according to the SSM message, and then forwards the SSM message to the downstream device. The SSM message contains a 4-bit code, which can express 16 types of signals to indicate different quality levels.

Table 6-2 lists quality levels in the SSM message.

Table 6-2  SSM quality levels

S1 Bit (Bits 5 to 8)

SDH Synchronization Quality Level

0000

Not used.

0001

Reserved. See Note 1.

0010

Stratum-1 clock. See Note 2.

0011

Reserved.

0100

Stratum-2 clock. See Note 3.

0101

Reserved.

0110

Reserved.

0111

Reserved.

1000

Stratum-3 clock.

1001

Reserved.

1010

Reserved.

1011

SDH clock (G813)

1100

Reserved.

1101

Reserved.

1110

Reserved.

1111

Not used for synchronization.

Note 1: Usage of the reserved codes depends on future application.

Note 2: This code is applicable to the V type clock defined in G.812 for SDH.

Note 3: This code is not applicable to the VI type clock defined in G.812 for SDH.

NOTE:

The S1 byte is transmitted through frames on the BITS interface and through SSM messages on the Ethernet.

Table 6-3 shows the mappings between international clock classes and Chinese clock classes.

Table 6-3  Mappings between international clock classes and Chinese clock classes

International Clock Class

Chinese Clock Class

QL-PRC

Stratum-1 clock

QL-SSU-T

Stratum-2 clock

QL-SSU-L

Stratum-3 clock

QL-SEC

SDH clock (G.813 Option I)

QL-DNU

Cannot be used to Synchronize.

BITS

The BITS clock is an accurate external clock.

The accuracy levels of clocks in descending order are: BITS clock, circuit clock, and clock generated by the local oscillator of the clock pinch board.

The clock pinch board provides two BITS interfaces, which can receive clock signals from two sources or obtain clock signals from the circuit.

Clock Source Selection Modes

The following clock sources can provide input clock signals:

  • External clock

  • Circuit clock

  • Oscillator of the clock pinch board

The device supports three clock source selection modes, as described in Table 6-4.

Table 6-4  Clock source selection modes

Mode

Description

Without the SSM quality level

  • This mode is used when the circuit clock or external clock does not provide the SSM quality level or when the quality level of each circuit clock source is already known. For example, if you know that the quality level of clock A is higher than the quality level of clock B, you can set a higher priority for clock A.

  • The system selects the clock source according to the priority that you set for each clock source. The clock source with the highest priority is selected.

With the SSM quality level

  • This mode is used when most of the circuit clock sources have SSM quality levels.

  • The system selects the clock source with the highest SSM quality level. When two clock sources have the same SSM quality level, the one with higher priority is selected.

Extended mode with the SSM quality

  • The system selects the clock source in the same way as the second mode.

  • The lower four bits of the S1 byte indicate the SSM quality level.

The higher four bits are used to transmit the clock source ID. The clock source ID prevents timing loops, where the output timing signal is sent back to the sender.

In the preceding modes, you can perform a manual or forcible switchover to select a specific clock.

  • In a manual switchover, you can change the clock source regardless of the clock source priority.

  • In a forcible switchover, you can change the clock source regardless of the clock source priority and SSM quality.

The selected clock signal will be sent to all LPUs through circuits on the backplane so that all LPUs obtain an accurate clock signal. The clock signal is then sent to the downstream network through interfaces on the LPUs.

Working Modes of the Clock Chip

The clock chip can work in any of the following modes:

  • Tracing

    If a BITS clock or circuit clock is selected as the clock source, the clock chip needs to trace and lock the clock frequency. This task is performed by the PLL.

  • Holding

    When tracing an external clock (a BITS clock or circuit clock), the clock chip keeps saving the data of the clock.

    When the clock cannot be used as the clock source, the clock chip maintains the frequency of the clock source for a certain period (24 hours at most) according to the clock data saved previously.

    In permanent holding mode, the clock chip uses the last saved data as the output clock frequency.

  • Free running

    In free running mode, the clock chip uses the clock generated by the oscillator as the external clock.

Common Clock Transmission Networking Modes

Table 6-5  Clock transmission networking modes

Networking Mode

Usage

Circuit clock transmitted downstream

  • The clock module obtains high-accuracy clock signals from the circuit and sends the clock signals to the downstream network.
  • The equipment uses the high-accuracy clock signals obtained from the circuit.

BITS clock to circuit clock

  • A BITS clock generates high-accuracy clock signals.
  • The high-accuracy clock signals are transmitted through the Ethernet.
  • The equipment uses the high-accuracy clock signals obtained from the BITS clock.

Circuit clock to BITS clock

  • The clock module obtains high-accuracy clock signals from the circuit.
  • A BITS clock generates high-accuracy clock signals.
  • The equipment uses the high-accuracy clock signals obtained from the circuit.

SSM Message Transmission on the Ethernet

The SSM quality level is transmitted on the Ethernet through SSM messages. Generally, an interface sends an SSM message every second. If the interface does not receive any SSM message from the peer interface within five seconds, the system considers that the SSM quality level of the circuit on the peer interface is Do not use (DNU). That is, the clock of this circuit will not be selected.

The Ethernet type value in an SSM message is 0x8809, indicating that the SSM protocol is a slow protocol. Figure 6-2 shows the format of an SSM message.

Figure 6-2  Format of an SSM message in an Ethernet frame

The fields in the SSM message are described as follows:

  • The value of the ITU Subtype field is 0x0001.

  • The value of the Version field is 1.

  • The Event Flag field indicates whether an event is reported and the value is 0.

  • The Data and Padding field uses the TLV structure. The first TLV contains the SSM quality level, as shown in Figure 6-3.

Figure 6-3  Format of the first TLV

The minimum length of the Data and Padding field is 64 bytes.

SSM Message Transmission in the BITS

The G.704 standard specifies that the SSM quality level should be transmitted in timeslot TS0 in the 2048 kbit/s multiframe. Figure 6-4 shows the structure of a 2048 kbit/s multiframe.

Figure 6-4  Structure of a 2048 kbit/s multiframe

A multiframe consists of eight sub-multiframes. If the SA4 bit is used to transmit the SSM quality level, each sub-multiframe transmits an SA4 bit. The eight sub-multiframes jointly carry a byte, which is called the S1 byte. The fifth to eighth bits of the S1 byte indicate the SSM quality level. You can specify the bit from which the clock module obtains the S1 byte.

Timing Loop Prevention

A timing loop occurs when the output signal of a clock becomes its own input signal. Measures should be taken in the network design stage to prevent timing loops. Timing loops can be prevented in the following ways:

  • When a circuit clock is selected as the clock source, you can set the SSM quality level of the clock to DNU to prevent timing loops that may occur on the peer device.

Figure 6-5  Timing loop prevention

  • Use the extended clock source selection mode with the SSM quality level.

    This mode is developed by Huawei and has been used as a standard in China. Implementation of this mode is as follows:

    • On the synchronization Ethernet, the SSM quality level occupies only the lower four bits of the S1 byte and the higher four bits are idle. The ID of the clock source is transmitted through the higher four bits of the S1 byte.

    • In a simple ring network, the reverse path of the ring network will transmit clock signals if the path of the ring network is down. The ID of the clock source can prevent timing loops by signing the primary clock source so that the clock source is protected.

    • On a complicated network, clock source IDs cannot completely eliminate timing loops because there are only 16 clock source IDs. In addition, the timing loops generated on a subnet that does not contain the origin clock source cannot be prevented. To prevent timing loops more effectively, use the clock source IDs to separate the subnets. A complicated network can be divided into two or more subnets.

    • On a subnet, the clock source IDs are allocated by the network designer.

Figure 6-6 is an example of subnetting.

Figure 6-6  Subnetting

Figure 6-6 shows a common networking mode, in which two rings are connected through two links. There are two available reference clock sources on the entire network. If you set IDs only for the two reference clock sources, the IDs cannot be terminated on the right ring when the links between the two rings fail because the IDs come from the left ring. In this case, a timing loop occurs.

The solution is as follows:

Divide the network into two subnets, namely, left ring and right ring.

  • Specify the master and slave BITS clocks on the left ring and set IDs for the BITS clocks.

  • Specify the two links as the master and slave reference clock sources for the right ring.

By setting clock source IDs, you can separate the left and right rings logically. On network element C on the right ring, set an ID for link a. Similarly, set an ID for link b on network element D. If faults occur on link a and link b, no timing loop is generated because the right ring has clock source IDs.

NOTE:

The clock source IDs set on the right ring identify the reference clock sources and separate the right ring from the left ring. The clock source IDs set on the left ring cannot be sent to the right ring through link a and link b, and the right ring can receive only the SSM quality level from the left ring.

The clock source IDs configured on the right ring can be the same as the IDs configured on the left ring, creating a greater number of possible IDs.

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Updated: 2019-08-21

Document ID: EDOC1000142080

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