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S12700 V200R010C00 Configuration Guide - Device Management

This document describes the principles and configurations of the Device Management features, and provides configuration examples of these features.
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Licensing Requirements and Limitations for Ethernet Clock Synchronization

Licensing Requirements and Limitations for Ethernet Clock Synchronization

Involved Network Elements

BITS clock source

Licensing Requirements

Ethernet clock synchronization is not under license control.

Version Requirements

Table 6-6  Applicable product models and versions

Product

Product Model

Software Version

S12700

S12704, S12708, S12710, and S12712

V200R010C00 and V200R011C10

NOTE:
To know details about software mappings, see Hardware Query Tool.

Feature Limitations

Constraints on Ethernet Clock Synchronization

  • To use the Ethernet clock synchronization feature, you must install the CKM-clock daughter card on the switch.
  • Only the X series (except the ET1D2G48TX1E card) support Ethernet clock synchronization. On the X1E series cards, the function takes effect only after the enhanced working mode is configured using the set service-mode command.
  • Ethernet clock synchronization is not supported on GE electrical interfaces, including GE combo interfaces that work in electrical interface mode.

Clock Sources Supported by the Switch

The device can transmit clock signals on the Ethernet or synchronous digital hierarchy (SDH) network. Table 6-7 lists types of clock sources supported by the switch.

Table 6-7  Supported clock sources

Clock No.

Name

Description

0

Inner Clock

Clock signal generated by the local oscillator of the clock daughter card.

1

BITS0

Clock signal sent or received by the BITS0 interface of the master main control board on local device.

2

BITS1

Clock signal sent or received by the BITS1 interface of the master main control board on local device.

3

Slave Board BITS0

Clock signal sent or received by the BITS0 interface of the slave main control board on local device.

4

Slave Board BITS1

Clock signal sent or received by the BITS1 interface of the slave main control board on local device.

5

Left Frame Clock

Clock signal sent from the left side of the frame by the LPUs with smaller slot IDs.

  • On the S12704, LPUs in slot 1 to slot 2 send clock signals from the left side of the frame.
  • On the S12708, LPUs in slot 1 to slot 4 send clock signals from the left side of the frame.
  • On the S12710, LPUs in slot 1 to slot 5 send clock signals from the left side of the frame.
  • On the S12712, LPUs in slot 1 to slot 6 send clock signals from the left side of the frame.

6

Right Frame Clock

Clock signal sent from the right side of the frame by the LPUs with greater slot IDs.

  • On the S12704, LPUs in slot 3 to slot 4 send clock signals from the right side of the frame.
  • On the S12708, LPUs in slot 5 to slot 8 send clock signals from the right side of the frame.
  • On the S12710, LPUs in slot 6 to slot 10 send clock signals from the right side of the frame.
  • On the S12712, LPUs in slot 7 to slot 12 send clock signals from the right side of the frame.

7

FSU

Clock source on the flexible service unit (FSU). This clock source is reserved.

8

Slave Board FSU

Clock source on the FSU of the peer board (MPU). This clock source is reserved.

9

System Clock

System clock.

10

Peer System Clock

System clock of the peer board (MPU).

The clock sources are described as follows:

  • The system clock, BITS0 clock, and BITS1 clock are external clocks used to synchronize clock signals. Only external clocks need to select the clock source.
  • An external clock can function as the reference clock source of other clocks or send clock signals. Other clocks can function only as the reference clock of external clocks.
  • The system clock can select the reference clock source among clocks 0 to 8.
  • The BITS clocks can select clocks 5 to 9 as the reference clock source.

Clock Source Selection Mode Supported by the Device

The device supports the following modes of clock source selection:

  • Free running
    • Non-SSM mode: The clock source is selected based on the priority. A smaller priority level indicates a higher priority.

    • SSM mode: The clock source is selected based on the SSM quality level and priority.

      The SSM quality level takes precedence over the priority in clock source selection.

      The clock source with the highest SSM quality level is selected first.

      When two clock sources have the same SSM quality level, the one with higher priority is selected.

    • SSM extended mode: This mode is based on the SSM mode, and you can set the clock ID in this mode.
  • Forcible mode
  • Manual mode

The SSM quality level takes precedence over the priority when the SSM quality level is used in clock source selection. In forcible mode, you can specify a clock source regardless of the SSM quality level and priority of the clock source. In manual mode, you can specify a clock source regardless of the priority of the clock source, but the SSM quality level still affects the selection result.

If you enable the result of frequency offset check to affect clock source selection, the selection result also depends on the result of frequency offset check. If the frequency offset of a clock is out of the specified range, the signal of the clock is considered invalid (Signal-fail), and the clock cannot be selected as the clock source.

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Updated: 2019-08-21

Document ID: EDOC1000142080

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