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S12700 V200R010C00 Configuration Guide - Device Management

This document describes the principles and configurations of the Device Management features, and provides configuration examples of these features.
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Example for Selecting the Clock Source Based on the SSM Quality Level in Extended Mode

Example for Selecting the Clock Source Based on the SSM Quality Level in Extended Mode

Networking Requirements

If the clock signal sent from the local device is sent back to the local device directly or through the network, a timing loop occurs. In extended SSM mode, you can set IDs for the circuit or external clock sources to prevent timing loops.

As shown in Figure 6-9, three switches form a ring network. SwitchC is connected to the primary clock. The Switches synchronize their clocks with the primary clock. Timing loops must be prevented through configuration.

Figure 6-9  Networking diagram for Selecting the Clock Source Based on the SSM Quality Level in Extended Mode

Configuration Roadmap

The configuration roadmap is as follows:
  1. Configure the routing protocol to make the IP routes between the nodes reachable.
  2. Configure the primary clock as the input clock source of SwitchA and set the ID of the reference clock source.
  3. Set the mode of clock source selection on SwitchB and SwitchC.

Procedure

  1. On SwitchA, enable the extended SSM mode and set the ID of the BITS clock source.

    # Enable the extended SSM mode. Set the ID of the BITS0 clock to 1 and the priority of the BITS0 clock to 1.

    <HUAWEI> system-view
    [HUAWEI] sysname SwitchA
    [SwitchA] clock ql-enable extend
    [SwitchA] clock id 1 source 1
    [SwitchA] clock priority 1 source 1 system

    # View the clock information on SwitchA, and you can see that the inner clock and system clock provide clock signals normally.

    [SwitchA] display clock priority 
    Reference Clock Source        System         bits0          bits1               
    ---------------------------------------------------------------------           
    0         Inner Clock         254            -              -                   
    1         BITS0               1              -              -                   
    2         BITS1               255            -              -                   
    3         Slave Board BITS0   255            -              -                   
    4         Slave Board BITS1   255            -              -                   
    5         Left Frame Clock    255            255            255                 
    6         Right Frame Clock   255            255            255                 
    7         System Clock        -              254            254
    

    # Verify that the SSM quality level is used in clock source selection.

    [SwitchA] display clock mode
    QL-Enable  : Yes (Extend Mode).
    Freq-Check : No.
    Retrieve   : Yes.
    Hold Type  : Hold 24 hours.
    Run Mode   : Free.
    Bits0      : Locked.
    Bits1      : Locked.
    System mode: Auto select clock source 1: BITS0.
    Bits0 mode : Auto select clock source 9: System Clock.
    Bits1 mode : Auto select clock source 9: System Clock.
    Clock time : Free-run
    

    # Verify that the system clock selects the inner clock as the clock source and that the system clock sends the clock signal to the LPUs as the output clock signal.

    [SwitchA] display clock selection
    Type                         Clock Source Selected
    ---------------------------------------------------------------------
    system                        1.    BITS0
    bits0                         9.    System Clock
    bits1                         9.    System Clock
    

  2. Set the mode of clock source selection on SwitchB.

    # On SwitchB, set the priority of the clock signal that GigabitEthernet5/0/7 sends from the right side of the frame to 10, and set priority of the clock signal that GigabitEthernet5/0/3 sends from the right side of the frame to 20. Retain the default WTR time. Set the priority of the clock signal sent from the right side of the frame to 6.
    NOTE:

    If you want to see the clock source switching result during debugging, set the WTR time to 0.

    <HUAWEI> system-view
    [HUAWEI] sysname SwitchB
    [SwitchB] clock ql-enable extend
    [SwitchB] interface gigabitethernet 5/0/7
    [SwitchB-GigabitEthernet5/0/7] clock right-frame 10
    [SwitchB-GigabitEthernet5/0/7] quit
    [SwitchB] interface gigabitethernet 5/0/3
    [SwitchB-GigabitEthernet5/0/3] clock right-frame 20
    [SwitchB-GigabitEthernet5/0/3] quit
    [SwitchB] clock priority 6 source 6 system
    
    # View information about the clock sources sent from the right side of the frame. You can see that the clock source of GigabitEthernet5/0/7 is sent to the clock board, and the clock synchronization direction is shown by the red arrows in Figure 6-9.
    [SwitchB] display clock right-frame
    Interface                     Priority            Clock Signal Selected
    ---------------------------------------------------------------------
    GigabitEthernet5/0/3          20                  N
    GigabitEthernet5/0/7          10                  Y
    

    # View the clock information on SwitchB, and you can see that the inner clock, Right Frame Clock, and system clock provide clock signals normally.

    [SwitchB] display clock source
    Reference Clock Source        Signal Fail    S1 Byte     ID       SSM
    ---------------------------------------------------------------------
    0         Inner Clock         No             --          -        SEC
    1         BITS0               Yes            --          -        DNU
    2         BITS1               Yes            --          -        DNU
    3         Slave Board BITS0   Yes            --          -        DNU
    4         Slave Board BITS1   Yes            --          -        DNU
    5         Left Frame Clock    Yes            --          -        DNU
    6         Right Frame Clock   No             12          -        PRC
    7         System Clock        No             --          -        PRC
    

    # Verify that the SSM quality level is used in clock source selection.

    [SwitchB] display clock mode
    QL-Enable  : Yes (Extend Mode).
    Freq-Check : No.
    Retrieve   : Yes.
    Hold Type  : Hold 24 hours.
    Run Mode   : Trace.(SyncOK, Locked)
    Bits0      : Locked.
    Bits1      : Locked.
    System mode: Auto select clock source 6: Right Frame Clock.
    Bits0 mode : Auto select clock source 9: System Clock.
    Bits1 mode : Auto select clock source 9: System Clock.
    Clock time : Free-run
    

    # Ensure that the system clock selects the clock source sent from the right side of the frame as the clock source and that the system clock sends clock signal to the LPUs as the output clock signal.

    [SwitchB] display clock selection
    Type                         Clock Source Selected
    ---------------------------------------------------------------------
    system                        6.    Right Frame Clock
    bits0                         9.    System Clock
    bits1                         9.    System Clock
    

  3. Set the mode of clock source selection on SwitchC.

    # On SwitchC, set the priority of the clock signal that GigabitEthernet2/0/3 sends from the left side of the frame to 30, and set priority of the clock signal that GigabitEthernet2/0/0 sends from the left side of the frame to 40. Retain the default WTR time. Set the priority of the clock signal sent from the left side of the frame to 5.
    NOTE:

    If you want to see the clock source switching result during debugging, set the WTR time to 0.

    <HUAWEI> system-view
    [HUAWEI] sysname SwitchC
    [SwitchC] clock ql-enable extend
    [SwitchC] interface gigabitethernet 2/0/3
    [SwitchC-GigabitEthernet2/0/3] clock left-frame 30
    [SwitchC-GigabitEthernet2/0/3] quit
    [SwitchC] interface gigabitethernet 2/0/0
    [SwitchC-GigabitEthernet2/0/0] clock left-frame 40
    [SwitchC-GigabitEthernet2/0/0] quit
    [SwitchC] clock priority 5 source 5 system
    
    # View information about the clock sources sent from the left side of the frame. You can see that the clock source of GigabitEthernet2/0/3 is sent to the clock board, and the clock synchronization direction is shown by the red arrows in Figure 6-9.
    [SwitchC] display clock left-frame
    Interface                     Priority            Clock Signal Selected
    ---------------------------------------------------------------------
    GigabitEthernet2/0/0          40                  N
    GigabitEthernet2/0/3          30                  Y
    

    # View the clock information on SwitchC, and you can see that the inner clock, Left Frame Clock, and system clock provide clock signals normally.

    [SwitchC] display clock source
    Reference Clock Source        Signal Fail    S1 Byte     ID       SSM
    ---------------------------------------------------------------------
    0         Inner Clock         No             --          -        SEC
    1         BITS0               Yes            --          -        DNU
    2         BITS1               Yes            --          -        DNU
    3         Slave Board BITS0   Yes            --          -        DNU
    4         Slave Board BITS1   Yes            --          -        DNU
    5         Left Frame Clock    No             12          -        PRC
    6         Right Frame Clock   Yes            --          -        DNU
    7         System Clock        No             --          -        PRC
    

    # Verify that the SSM quality level is used in clock source selection.

    [SwitchC] display clock mode
    QL-Enable  : Yes (Extend Mode).
    Freq-Check : No.
    Retrieve   : Yes.
    Hold Type  : Hold 24 hours.
    Run Mode   : Trace.(SyncOK, Locked)
    Bits0      : Locked.
    Bits1      : Locked.
    System mode: Auto select clock source 5: Left Frame Clock.
    Bits0 mode : Auto select clock source 9: System Clock.
    Bits1 mode : Auto select clock source 9: System Clock.
    Clock time : Free-run
    

    # Ensure that the system clock selects the clock source sent from the left side of the frame as the clock source and that the system clock sends clock signal to the LPUs as the output clock signal.

    [SwitchC] display clock selection
    Type                         Clock Source Selected
    ---------------------------------------------------------------------
    system                        5.    Left Frame Clock
    bits0                         9.    System Clock
    bits1                         9.    System Clock
    

  4. Verify the configuration.

    The commands used to verify the configuration result are included in the preceding steps.

Configuration Files

  • SwitchA configuration file

    #
     sysname SwitchA
    #
     clock ql-enable extend
     clock id 1 source 1 
     clock priority 1 source 1 system 
    #
    
  • SwitchB configuration file

    #
     sysname SwitchB
    #
     clock ql-enable extend
     clock priority 6 source 6 system
    #
    interface GigabitEthernet5/0/3
     clock right-frame 20
    #
    interface GigabitEthernet5/0/7
     clock right-frame 10
    #
    
  • SwitchC configuration file

    #
     sysname SwitchC
    #
     clock ql-enable extend
     clock priority 5 source 6 system
    #
    interface GigabitEthernet2/0/0
     clock left-frame 40
    #
    interface GigabitEthernet2/0/3
     clock left-frame 30
    #
    
Translation
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Updated: 2019-08-21

Document ID: EDOC1000142080

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