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ME60 Troubleshooting Guide V1.0 (VRPv8)

This document provides the maintenance guide of the device, including daily maintenance, emergence maintenance, and typical troubleshooting.
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Huawei uses machine translation combined with human proofreading to translate this document to different languages in order to help you better understand the content of this document. Note: Even the most advanced machine translation cannot match the quality of professional translators. Huawei shall not bear any responsibility for translation accuracy and it is recommended that you refer to the English document (a link for which has been provided).
Troubleshooting for 1588v2

Troubleshooting for 1588v2

This section provides the flowchart and procedure for troubleshooting of the 1588v2 function.

Master Clock Selection Failure in BC or OC Mode

This section describes how to locate the fault that the master clock selection in 1588v2 BC or OC mode is faulty.

Common Causes

The master clock selection is faulty and the clock ID and interface status are incorrect, after a device is configured to work in 1588v2 BC or OC mode.

This fault is commonly caused by one of the following:

  • The physical link is faulty.

  • The device types of network elements are incorrect.

  • The clock domain values of network elements are incorrect.

  • The configurations of two directly connected interfaces are different.

  • The quality level of the slave clock is too low.

  • The master clock is configured to work in slave only state.

  • The local clock IDs of two network elements are the same.

Troubleshooting Flowchart

Figure 4-17 Troubleshooting flowchart for master clock selection failure

Troubleshooting Procedure

Procedure

  1. Check whether the physical link is normal.

    Run the display ptp all command on all network elements to check the interface status. If an interface is faulty, a fault may have occurred on a link or board. Check whether there is an hwPtpPortStateChange alarm, or run the display ptp all command on the device and Port info field shows that the State is faulty. If an interface is faulty, clear the link fault.

    Port info                                                                          
    Name                     State          Delay-mech Ann-timeout   Type   Domain  
    -------------------------------------------------------------------------------
    GigabitEthernet1/0/0        faulty        delay      3           BC     0

    If the problem persists, go to Step 2.

  2. Run the display ptp all command to check whether the device type of each network element along a link is correct.

    If the device type is incorrect, run the ptp device-type command to reconfigure the device type based on network planning.

    If the problem persists, go to Step 3.

  3. Run the display ptp all command on network elements to check whether the Domain value fields in the command outputs are the same.

    The network elements synchronize their clocks only when they are in the same clock domain. If the configuration is incorrect, run the ptp domain domain-value command based on network planning to configure the same domain value for each network element.

    If the problem persists, go to Step 4.

  4. Check whether configurations on the interfaces are consistent.

    1. Run the display ptp all config command to check configuration in each interface view and whether the packet encapsulation types on both interfaces of a link are the same. If the encapsulation types are different, run the ptp mac-egress or ptp udp-egress command to reconfigure them.

    2. Check whether an interface is forcibly configured with interface status. This means to check whether the Set port state field is yes. If the Set port state field is yes, run the display this in the interface view to check whether the ptp port-state command is configured. If the ptp port-state command is configured, reconfigure this command.

    If the problem persists, go to Step 5.

  5. Check whether the quality level of the clock source is appropriate.

    Run the display ptp all command to check whether the Class of a local clock in the Clock source info is less than 128. If the quality level of a clock is less than 128, the clock cannot be a slave clock. This means that the interface status cannot be Slave. Run the ptp clock-source local command to reconfigure the quality level.

    If the problem persists, go to Step 6.

  6. Run the display ptp all command to check the slave-only attribute of the Ordinary Clock (OC). If this attribute is yes, the OC cannot be a master clock. This means the interface status cannot be Master. Run the undo ptp slaveonly command to disable slave-only from the OC.

    If the problem persists, go to Step 7.

  7. Run the display ptp all command to check whether the Local clock ID of both network elements are the same. If they are the same, the master clock selection is faulty. Run the ptp virtual-clock-id command to reconfigure different Local clock ID for the network elements.

    If the problem persists, go to Step 8.

  8. Collect trap, log, and configuration information, and contact Huawei technical support personnel.
Relevant Alarms and Logs

PTP_1.3.6.1.4.1.2011.5.25.187.5.1_hwPtpPortStateChange

1588v2 Clock Source Selection Is Correct, But Time and Frequency Tracing Precision Does Not Meet 1588v2 Clock Performance Requirements

Common Causes

This section describes common causes for this fault.

This fault is commonly caused by one of the following:

  • The clock does not work in the tracing state.

  • The P/E modes of the PTP interfaces at both ends of the link are different.

  • The receive and transmit optical fibers have different lengths, and no 1588v2 transmission asymmetry correction is configured.

Troubleshooting Procedure

This section describes how to troubleshoot this fault.

Procedure

  1. Check that the clock works in the tracing state, that is, check that System trace source State in the display clock source command output is lock mode.

    Run the display clock source command to check whether System trace source State is lock mode.

    • If System trace source State is not lock mode, run the display clock config command to check whether sys pll is clock select mode auto.

      • If sys pll is not clock select mode auto, run the clock run-mode normal command in the system view to set the clock running mode to normal.
      • If sys pll is clock select mode auto, configure frequency source synchronization. If you specify PTP synchronization, a device synchronizes frequency based on 1588v2 clock source selection results. If you specify physical-layer synchronization, a device synchronizes frequency based on physical-layer clock source selection results. For details, see the chapter "1588v2 Configuration" in the Configuration - System Management or "Clock Synchronization Configuration" in the Configuration - Basic Configurations.
    • If System trace source State is lock mode, go to Step 2.

  2. Check that the P/E modes of the PTP interfaces at both ends of the link are the same, that is, check that Delay-mech in the display ptp all command output is the same at both ends.

    Run the display ptp all command at both ends respectively to check whether Delay-mech is the same.

    • If Delay-mech is different, the interface status is normal but time is not synchronized. Run the ptp delay-mechanism { delay | pdelay } command on the interface view to set the same delay mechanism at both ends.
    • If Delay-mech is the same, go to Step 3.

  3. Check that 1588v2 transmission asymmetry correction is configured for all devices.

    1588v2 transmission asymmetry correction is configured only when the receive and transmit optical fibers have different lengths. If the receive and transmit optical fibers have the same length, configuring 1588v2 transmission asymmetry correction causes time not to be synchronized.

    • If the receive and transmit optical fibers have different lengths and no 1588v2 transmission asymmetry correction is configured, run the ptp asymmetry-correction command in the interface view to configure an asymmetry correction time in ns.
    • If the receive and transmit optical fibers have the same length or 1588v2 transmission asymmetry correction has been configured, go to Step 4.

  4. Collect the following information and contact Huawei technical support personnel.

    • Results of the troubleshooting procedure

    • Configuration files, log files, and alarm files of the devices

Relevant Alarms and Logs

This section describes alarms and logs related to this fault.

Relevant Alarms

None

Relevant Logs

None

External Clock Source Cannot Be Tracked

Common Causes

This section describes common causes of the fault that the external clock source cannot be tracked.

An external clock interface can be configured to input or output clock signals. If the external clock interface is configured to input clock signals, the device synchronizes its own clock with the external clock source. If the external clock interface is configured to output clock signals, the device export clock signals to another device for synchronization.

When the external clock interface is configured to input clock signals, the external clock source may fail to be tracked.

This fault is commonly caused by one of the following:

  • The signal type configured on the local device is different from that configured on the external clock source.

  • The TOD protocol configured on the local device is different from that on the external clock source when 1PPS+TOD is adopted.

  • The external clock source cannot be tracked.

  • The physical-layer frequency synchronization is not adopted.

Troubleshooting Procedure

This section describes the troubleshooting procedure for the fault that the external clock source cannot be tracked.

Procedure

  1. Check whether the external clock interface is in the normal state.

    Run the display ptp all command to check whether the In-status is normal.

    • If In-status is normal, go to step 7.
    • If In-status is abnormal, go to step 2.

  2. Check whether the signal type configured on the local device is same with that configured on the external clock source.

    Run the display clock config command to check whether the signal type configured on the local device is the same as that configured on the external clock source.

    • If the local device and external clock source have different signal types, run the clock bits-type { bits0 | bits1 | bits2 } { dcls | 1pps { input | output } } in the system view to configure the signal type of the external clock source as the same as that of the local device.
    • If the local device and external clock source have the same signal type, check whether the cable is properly connecting the local device to the external clock source.

    If the problem persists, go to Step 3.

  3. Perform the following operations based on the signal type.

    • If 1PPS+TOD is adopted, go to Step 4.
    • If DCLS is adopted, go to Step 7.

  4. Check whether the TOD protocol configured on the local device is the same as that configured on the external clock source.

    Run the display clock config command to check whether the TOD protocol configured on the local device is same with that configured on the external clock source. The clock synchronization can be implemented only when the same TOD protocol is configured on both the local device and external clock source.

    • If the TOD protocols configured on the local device and external clock source are different, run the clock tod protocol { ubx | nmea | ccsa } command to configure the TOD protocol on the local device as the same as that on the external clock source.
    • If the TOD protocols are consistent, go to step 5.

  5. Check whether the external clock source can be tracked.

    Run the display clock source command to check whether System trace source State is lock mode.

    NOTE:
    When System trace source State is not lock mode, the external clock source exports invalid time signals. As a result, the clock synchronization fails.
    • If System trace source State is not lock mode, run the display clock config command to check whether sys pll is auto mode.

      • If sys pll is not auto mode, run the clock run-mode normal command in the system view to set the clock running mode to normal.
      • If sys pll is auto mode, configure frequency source synchronization. If you specify PTP synchronization, the device synchronizes frequency based on 1588v2 clock source selection results. If you specify physical-layer synchronization, the device synchronizes frequency based on physical-layer clock source selection results. For details, see the chapter "1588v2 Configuration" in the Configuration - System Management or "Clock Synchronization Configuration" in the Configuration - Basic Configurations.
    • If System trace source State is lock mode, go to Step 6.

  6. Check whether priorities of external clock sources are configured on the external clock interface.

    NOTE:

    When the external clock interface is configured to input clock signals, the physical-layer frequency synchronization must be adopted. The frequency synchronization must be implemented so that the clock synchronization can be implemented. Otherwise, the clock synchronization will fail. Priorities of external clock sources must be configured on the external clock interface so that the physical-layer frequency synchronization can be implemented.

    Run the display this command in the system view to check whether the clock priority command is configured.

    • If the clock priority command is not configured, run the clock priority priority-value command to set priorities of external clock sources.
    • If the clock priority command is not configured, go to Step 7.

  7. Collect the following information and contact Huawei technical support personnel.

    • Results of the troubleshooting procedure.
    • Configuration files, log files, and alarm files of the devices

Relevant Alarms and Logs

This section describes relevant alarms and logs for the fault that the external clock source cannot be tracked.

Relevant Alarms

None

Relevant Logs

None

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Updated: 2019-06-11

Document ID: EDOC1000175918

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