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Command Reference

S7700 and S9700 V200R011C10

This document describes all the configuration commands of the device, including the command function, syntax, parameters, views, default level, usage guidelines, examples, and related commands.
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Clock Syntonization Commands

Clock Syntonization Commands

Command Support

Commands provided in this section and all the parameters in the commands are supported by all switch models by default, unless otherwise specified. For details, see specific commands.

clock 1pps-tod

Function

The clock 1pps-tod command sets the format of 1 pps-tod.

The undo clock 1pps-tod command restore the default format of 1 pps-tod.

By default, the format of 1 pps-tod is RS232.

Format

clock 1pps-tod { rs232 | gps }

undo clock 1pps-tod [ rs232 | gps ]

Parameters

Parameter

Description

Value

rs232

This object indicates that the format of 1 pps-tod is RS232.

-

gps

This object indicates that the format of 1 pps-tod is GPS.

-

Views

System view

Default Level

2: Configuration level

Usage Guidelines

1 pps-tod has RS232 and GPS formats. You can use the clock 1pps-tod command to set the format of 1 pps-tod.

If the time signal type is set to 1 pps-tod using the clock bits-type command on the sender and receiver of time signals, ensure that the sender and receiver use the same 1 pps-tod format (both use RS232 or GPS format).

Example

# Set the time signal type to 1 pps-tod (GPS format).

<HUAWEI> system-view
[HUAWEI] clock 1pps-tod gps

clock bits-type

Function

The clock bits-type command sets the transmission mode of clock syntonization and time synchronization of a BITS clock.

The undo clock bits-type command deletes the configured transmission mode.

By default, a BITS clock works in bps-2m mode.

Format

clock bits-type { bps-2m | bps-1544m | hz-2m } { bits0 | bits1 }

clock bits-type { dcls-time | 1pps-tod } { in | out } { bits0 | bits1 }

undo clock bits-type [ bps-2m | bps-1544m | hz-2m ] { bits0 | bits1 }

undo clock bits-type [ { dcls-time | 1pps-tod } { in | out } ] { bits0 | bits1 }

Parameters

Parameter

Description

Value

bps-2m

Sets the transmission rate of the clock information from the external BITS clock to 2 Mbit/s.

-

hz-2m

Sets the transmission frequency of the clock information from the external BITS clock to 2 MHz.

-

bps-1544m

Sets the transmission rate of the clock information from the external BITS clock to 1.544 Mbit/s.

-

dcls-time

Sets the time of the external BITS clock to the DC Level Shifter (DCLS) time, which is an external time.

-

1pps-tod

Sets the time of the external BITS clock to 1 pps Time of Day (TOD), which is an external time.

-

in

Indicates that the external clock is the input clock, that is, synchronizes the time from the external clock to the local clock.

-

out

Indicates that the external clock is the output clock, that is, synchronizes the time from the local clock to the external clock.

-

bits0

Indicates the first BITS clock, BITS0.

-

bits1

Indicates the second BITS clock, BITS1.

-

Views

System view

Default Level

2: Configuration level

Usage Guidelines

The clock bits-type command is applicable only to clock syntonization and time synchronization in BITS interfaces.

The clock bits-type { bps-2m | bps-1544m | hz-2m } { bits0 | bits1 } command sets the clock mode.

The clock bits-type { dcls-time | 1pps-tod } { in | out } { bits0 | bits1 } command sets the time mode.

In clock syntonization mode, the clock information is transmitted bidirectionally.

If the clock syntonization mode is set to BPS (bps-2m or bps-1544m) and if the quality level of the Synchronization Status Message (SSM) is used in clock source selection, the BITS clocks can obtain the quality level of the clock automatically. When the clock syntonization mode is set to other modes, such as hz-2m, the BITS clocks cannot obtain the SSM quality level. In this case, if quality level is required in clock source selection, you need to run the clock ssm-config command to set the SSM quality level.

In time synchronization mode (dcls-time or 1pps-tod), you need to specify the transmission direction of the clock information (in or out).

Example

# Configure the BITS0 interface to transmit the clock information at a frequency of 2 MHz.

<HUAWEI> system-view
[HUAWEI] clock bits-type hz-2m bits0 

# Display information about the BITS0 clock.

<HUAWEI> display clock bits0
Type: 2M hz.
Recv sa-bit: SA4.
Send sa-bit: SA4.
Force out s1: No
ID out: Yes   
Related Topics

clock clear-switch

Function

Using the clock clear-switch command, you can cancel the clock source switchover to restore the automatic running status of the clock for system to select the clock source automatically.

By default, the system automatically selects the clock source.

Format

clock clear-switch { bits1 | bits0 | system }

Parameters

Parameter

Description

Value

bits0

Configures the BITS0 clock to select the clock source automatically.

-

bits1

Configures the BITS1 clock to select the clock source automatically.

-

system

Configures the system clock to select the clock source automatically.

-

Views

System view

Default Level

2: Configuration level

Usage Guidelines

The clock clear-switch command cancels the manual clock source switchover configured by the clock manual-switch command and the forced clock source switchover configured by the clock force-switch command.

Example

# Cancel the forced clock source switchover.

<HUAWEI> system-view
[HUAWEI] clock clear-switch bits0

clock extern-time out

Function

The clock extern-time out command configures a BITS interface as the sender of time signals, and sets the time type.

The undo clock extern-time out command deletes the configured time type.

By default, a BITS interface is not configured as the sender of time signals.

Format

clock extern-time out { dcls-time | 1pps-tod }

undo clock extern-time out [ dcls-time | 1pps-tod ]

Parameters

Parameter

Description

Value

dcls-time

Sets the time of the external BITS clock to the DC Level Shifter (DCLS) time, which is an external time.

-

1pps-tod

Sets the time of the external BITS clock to 1 pps-tod, which is an external time.

-

Views

System view

Default Level

2: Configuration level

Usage Guidelines

This command is required only when the BITS interface needs to send the time signal.

NOTE:

1pps-tod (RS232 format) and 1pps-tod (GPS format) are the same time type of different formats.

If the time signal type is set to 1 pps-tod on the sender and receiver of time signals, set the same format of 1 pps-tod on the sender and receiver (both use RS232 or GPS format).

When a BITS clock needs to send time signals, perform the following steps:
  1. Run the clock bits-type { dcls-time | 1pps-tod } { in | out } { bits0 | bits1 } command to set the type of the output time signal for the BITS interface.
  2. Run the clock extern-time out { dcls-time | 1pps-tod } command to set the type of the input time signal to the time board.
  3. (Optional) Run the clock 1pps-tod { rs232 | gps } command to set the type of 1pps-tod.

Example

# Configure the BITS1 interface to send the time signal of the 1pps-tod type.

<HUAWEI> system view
[HUAWEI] clock bits-type 1pps-tod out bits1

# Set the type of the output time signal to 1pps-tod (GPS format).

[HUAWEI] clock extern-time out 1pps-tod
[HUAWEI] clock 1pps-tod gps

clock force-out-s1 (System view)

Function

The clock force-out-s1 command sets the synchronization status message code (S1 byte) sent by the BITS clock.

The undo clock force-out-s1 command cancels the setting of the S1 byte.

By default, the S1 byte is set automatically according to the SSM of the selected clock source.

Format

clock force-out-s1 { s1-prc | s1-ssu-t | s1-ssu-l | s1-sec | s1-dnu | else-s1-byte } { bits0 | bits1 }

undo clock force-out-s1 [ s1-prc | s1-ssu-t | s1-ssu-l | s1-sec | s1-dnu | else-s1-byte ] { bits0 | bits1 }

Parameters

Parameter

Description

Value

s1-prc

Sets the S1 byte for the stratum-1 clock.

0x2

s1-ssu-t

Sets the S1 byte for the stratum-2 clock.

0x4

s1-ssu-l

Sets the S1 byte for the stratum-3 clock.

0x8

s1-sec

Sets the S1 byte for the synchronous digital hierarchy (SDH) clock.

0xb

s1-dnu

Indicates not to use the S1 byte in clock syntonization.

0xf

else-s1-byte

Sets the S1 byte to other values.

The value is a hexadecimal number that ranges from 0 to FF.

bits0

Indicates the first BITS clock, BITS0.

-

bits1

Indicates the second BITS clock, BITS1.

-

Views

System view

Default Level

2: Configuration level

Usage Guidelines

Normally, the clock module sets the S1 byte according to the SSM level of the clock source.

NOTE:

This command is used for debugging and is not recommended in normal cases.

Example

# Set the S1 byte sent by the BITS0 clock to 11.

<HUAWEI> system-view
[HUAWEI] clock bits-type hz-2m bits0
[HUAWEI] clock force-out-s1 11 bits0

# Display information about the BITS0 clock.

<HUAWEI> display clock bits0
Type: 2M bps.
Recv sa-bit: SA4.
Send sa-bit: SA4.
Recv s1 byte: 0x0f.
Send s1 byte: 0x11.
Force out s1: Yes, The s1 byte configed is:0x11.
ID out: Yes              

# Cancel the setting of the S1 byte sent by the BITS0 clock.

<HUAWEI> system-view
[HUAWEI] undo clock force-out-s1 bits0
[HUAWEI] display clock bits0
Type: 2M bps.
Recv sa-bit: SA4.
Send sa-bit: SA4.
Recv s1 byte: 0x0f.
Send s1 byte: 0x0f.
Force out s1: No
ID out: Yes  
Related Topics

clock force-out-s1 (interface view)

Function

The clock force-out-s1 command sets the synchronization status message code (S1 byte) sent by an interface.

The undo clock force-out-s1 command cancels the setting of the S1 byte.

By default, the S1 byte is set automatically according to the SSM level of the selected clock source.

Format

clock force-out-s1 { s1-prc | s1-ssu-t | s1-ssu-l | s1-sec | s1-dnu | else-s1-byte }

undo clock force-out-s1 [ s1-prc | s1-ssu-t | s1-ssu-l | s1-sec | s1-dnu | else-s1-byte ]

Parameters

Parameter

Description

Value

s1-prc

Sets the S1 byte for the stratum-1 clock.

0x2

s1-ssu-t

Sets the S1 byte for the stratum-2 clock.

0x4

s1-ssu-l

Sets the S1 byte for the stratum-3 clock.

0x8

s1-sec

Sets the S1 byte for the SDH clock.

0xb

s1-dnu

Indicates not to use the S1 byte in clock syntonization.

0xf

else-s1-byte

Sets the S1 byte to other values.

The value is a hexadecimal number that ranges from 0 to FF.

Views

GE interface view, XGE interface view, 40GE interface view, 100GE interface view

Default Level

2: Configuration level

Usage Guidelines

Normally, the clock module sets the S1 byte according to the SSM level of the clock source.

NOTE:

This command is used in special networking and is not recommended in normal cases.

This command is invalid on a GE electrical interface.

Example

# Set the S1 byte sent by GigabitEthernet1/0/0 to 12.

<HUAWEI> system-view
[HUAWEI] interface gigabitethernet 1/0/0
[HUAWEI-GigabitEthernet1/0/0] clock force-out-s1 12

# Display the clock information on GigabitEthernet1/0/0.

<HUAWEI> display clock state interface gigabitethernet 1/0/0
Priority: 255.
Send S1: 12, Send SSM: PRC.
Force Out S1: Yes, The s1 byte is: 0x12.
Id-out: Yes.              
Related Topics

clock force-switch

Function

The clock force-switch command forcibly switches the clock source of a clock.

The undo clock force-switch command restores the automatic selection of the clock source.

By default, the system automatically selects the clock source.

Format

clock force-switch source source { system | bits0 | bits1 }

undo clock force-switch source source { system | bits0 | bits1 }

Parameters

Parameter

Description

Value

source source

Specifies the reference clock source for the system clock or BITS clock.

source specifies the number of a clock source.

The value is an integer that ranges from 0 to 8 for the clock source of the system clock and 5 to 9 for the clock source of the BITS clock.

The mappings between the clock source numbers and clock sources are as follows:

  • 0: Inner Clock, that is, the clock generated by the local oscillator, which cannot be changed
  • 1: BITS0, that is, the BITS0 clock
  • 2: BITS1, that is, the BITS1 clock
  • 3: Slave Board BITS0, that is, the BITS0 clock on the slave board
  • 4: Slave Board BITS1, that is, the BITS1 clock on the slave board
  • 5: Left Frame Clock, that is, the clock signal sent from the left side of the frame
  • 6: Right Frame Clock, that is, the clock signal sent from the right side of the frame
  • 7: FSU, that is, the clock on the FSU
  • 8: Slave Board FSU, that is, the clock on the peer FSU
  • 9: System Clock, that is, the clock selected automatically or specified by forcible switchover or manual switchover

system

Indicates the clock source of the system clock.

-

bits0

Indicates the clock source of the BITS0 clock.

-

bits1

Indicates the clock source of the BITS1 clock.

-

Views

System view

Default Level

2: Configuration level

Usage Guidelines

The clock source can be selected in automatic, manual, or forcible mode. In automatic mode, the system selects the clock source depending on whether the SSM quality level is used in the selection.

In forcible mode, you can change the clock source regardless of the priority and quality level of the clock source.

NOTE:

Forcible switchover of the clock source fails in any of the following conditions:

  • The priority of the specified clock source is set to DIS (255) by the undo clock priority command.

  • The specified clock source is locked by the clock lockout command.

  • The number of the source clock of the system clock ranges from 0 to 8.

  • The number of the source clock of the BITS clock ranges from 5 to 9.

If you run the clock manual-switch command, the clock source selection mode changes from forcible mode to manual mode.

If you run the clock clear-switch command, the clock source selection mode changes from forcible switchover to automatic mode.

Example

# Forcibly change the clock source of the BITS0 clock to clock source 9.

<HUAWEI> system-view
[HUAWEI] clock force-switch source 9 bits0
[HUAWEI] display clock mode
QL-Enable  : No.
Freq-Check : No.
Retrieve   : Yes.
Hold Type  : Hold 24 hours.
Run Mode   : Trace.
Bits0      : Locked.
Bits1      : Locked.
System mode: Auto select clock source 0: Inner Clock.
Bits0 mode : Force-switch clock source 9: System Clock (Actual: 9: System Clock).
Bits1 mode : Auto select clock source 9: System Clock.
Clock time : Free-run

# Forcibly change the clock source of the BITS0 clock to clock source 8, which is locked.

[HUAWEI] display clock lockout
Reference Clock Source        System         Bits0          Bits1
---------------------------------------------------------------------
0         Inner Clock         No             -              -
1         BITS0               No             -              -
2         BITS1               No             -              -
3         Slave Board BITS0    No             -              -
4         Slave Board BITS1    No             -              -
5         Left Frame Clock    No             No             No
6         Right Frame Clock   No             No             No
7         FSU                 No             No             No
8         Slave Board FSU      No             Yes            No
9         System Clock        -              No             No     
[HUAWEI] clock force-switch source 8 bits0
clock-source #8 is Locked Out! cannot switch! 

clock freq-check

Function

Using the clock freq-check command, you can enable frequency offset check to affect clock source selection.

Using the undo clock freq-check command, you can disable frequency offset check from affecting clock source selection.

By default, the result of frequency offset check does not affect clock source selection.

Format

clock freq-check

undo clock freq-check

Parameters

None

Views

System view

Default Level

2: Configuration level

Usage Guidelines

After you run the undo clock freq-check command, the system still calculates the frequency offset of clocks, but the calculation result does not affect clock source selection.

Example

# Enable frequency offset check to affect clock source selection.

<HUAWEI> system-view
[HUAWEI] clock freq-check

# Disable frequency offset check from affecting clock source selection.

<HUAWEI> system-view
[HUAWEI] undo clock freq-check

clock freq-check-range

Function

Using the clock freq-check-range command, you can set the valid range of clock frequency offset in frequency offset check.

Using the undo clock freq-check-range command, you can restore the default range of clock frequency offset in frequency offset check.

By default, the maximum left frequency offset is -9.2 ppm, the maximum right frequency offset is 9.2 ppm.

Format

clock freq-check-range left-range right-range

undo clock freq-check-range [ left-range right-range ]

Parameters

Parameter

Description

Value

left-range

Specifies the maximum left frequency offset of the clock.

The value is an integer that ranges from 50 to 1000.

The unit is -0.01 ppm.

By default, the maximum left frequency offset is -9.2 ppm.

right-range

Specifies the maximum right frequency offset of the clock.

The value is an integer that ranges from 50 to 1000.

The unit is 0.01 ppm.

By default, the maximum right frequency offset is 9.2 ppm.

Views

System view

Default Level

2: Configuration level

Usage Guidelines

If the frequency offset of a clock source is not in the specified range, it indicates that the frequency offset of the clock source is too large.

NOTE:

Change of the frequency offset range is not recommended.

Example

# Set the range of frequency offset.

<HUAWEI> system-view
[HUAWEI] clock freq-check-range 50 600

# Display the range of frequency offset.

[HUAWEI] display clock freq-check-range
Clock frequency check range: [-0.50 ppm, 6.00 ppm].

# Restore the default range of frequency offset.

[HUAWEI] undo clock freq-check-range
[HUAWEI] display clock freq-check-range
Clock frequency check range: [-9.20 ppm, 9.20 ppm].

clock hold-for-ever

Function

Using the clock hold-for-ever command, you can configure the clock module to hold the previous clock information permanently when all the clock sources are lost.

Using the undo clock hold-for-ever command, you can restore the default holding mode, that is, the 24-hour holding mode.

By default, the clock module holds the previous clock information for 24 hours when all the clock sources are lost.

Format

clock hold-for-ever

undo clock hold-for-ever

Parameters

None

Views

System view

Default Level

2: Configuration level

Usage Guidelines

When all the clock sources are lost, the clock module enters the holding state and retains the original frequency offset according to the clock information traced before.

In the 24-hour holding mode, the clock module enters the free running mode not more than 24 hours after all the clock sources are lost. In the free running mode, the clock module uses the clock signal generated by the local oscillator as the clock source.

Example

# Configure the permanent holding mode for the clock module.

<HUAWEI> system-view
[HUAWEI] clock hold-for-ever

# Display information about the clock module.

<HUAWEI> display clock mode
QL-Enable  : No.
Freq-Check : No.
Retrieve   : Yes.
Hold Type  : Hold for ever.
Run Mode   : Free.
Bits0      : Locked.
Bits1      : Locked.
System mode: Auto select clock source 0: Inner Clock.
Bits0 mode : Auto select clock source 9: System Clock.
Bits1 mode : Auto select clock source 9: System Clock.
Clock time : Free-run 

# Configure the 24-hour holding mode for the clock module.

<HUAWEI> system-view
[HUAWEI] undo clock hold-for-ever
[HUAWEI] display clock mode
QL-Enable  : No.
Freq-Check : No.
Retrieve   : Yes.
Hold Type  : Hold 24 hours.
Run Mode   : Free.
Bits0      : Locked.
Bits1      : Locked.
System mode: Auto select clock source 0: Inner Clock.
Bits0 mode : Auto select clock source 9: System Clock.
Bits1 mode : Auto select clock source 9: System Clock.
Clock time : Free-run 
Related Topics

clock hold-off-time

Function

Using the clock hold-off-time command, you can set the delay time for the system to consider a clock source lost.

Using the undo clock hold-off-time command, you can restore the default delay time.

By default, the delay time for the system to consider a clock source lost is 500 ms.

Format

clock hold-off-time hold-off-time source source

undo clock hold-off-time [ hold-off-time ] source source

Parameters

Parameter

Description

Value

hold-off-time

Specifies the delay time for the system to consider a clock source lost.

The value is an integer that ranges from 3 to 18. The unit is 100 ms.

By default, the delay time is 500 ms.

source source

Specifies the clock source.

source specifies the number of a clock source.

The value is an integer that ranges from 0 to 8.

The mappings between the clock source numbers and clock sources are as follows:

  • 0: Inner Clock, that is, the clock generated by the local oscillator, which cannot be changed
  • 1: BITS0, that is, the BITS0 clock
  • 2: BITS1, that is, the BITS1 clock
  • 3: Slave Board BITS0, that is, the BITS0 clock on the slave board
  • 4: Slave Board BITS1, that is, the BITS1 clock on the slave board
  • 5: Left Frame Clock, that is, the clock signal sent from the left side of the frame
  • 6: Right Frame Clock, that is, the clock signal sent from the right side of the frame
  • 7: FSU, that is, the clock on the FSU
  • 8: Slave Board FSU, that is, the clock on the peer FSU

Views

System view

Default Level

2: Configuration level

Usage Guidelines

The system considers a clock source lost after a delay time. Within the delay time, the system considers that the clock source exists.

Setting the delay time can avoid some mistakes in determining the clock source caused by occasional signal jitter on the network.

Example

# Set the delay time.

<HUAWEI> system-view
[HUAWEI] clock hold-off-time 3 source 1

# Display the delay time.

<HUAWEI> display clock hold-off-time
Reference      Clock Source                  Hold Off(unit:100ms)
-----------------------------------------------------------------
0              Inner Clock                   5
1              BITS0                         3
2              BITS1                         5
3              Slave Board BITS0              5
4              Slave Board BITS1              5
5              Left Frame Clock              5
6              Right Frame Clock             5
7              FSU                           5
8              Slave Board FSU                5

# Restore the default delay time.

<HUAWEI> system-view
[HUAWEI] undo clock hold-off-time source 1
[HUAWEI] display clock hold-off-time
Reference      Clock Source                  Hold Off(unit:100ms)               
---------------------------------------------------------------------           
0              Inner Clock                   5                                  
1              BITS0                         5                                  
2              BITS1                         5                                  
3              Slave Board BITS0             5                                  
4              Slave Board BITS1             5                                  
5              Left Frame Clock              5                                  
6              Right Frame Clock             5                                  
7              FSU                           5                                  
8              Slave Board FSU               5       

clock id

Function

Using the clock id command, you can set the ID of a clock source.

Using the undo clock id command, you can restore the default ID of a clock source.

By default, the ID of a clock source is 0.

Format

clock id id source source

undo clock id [ id ] source source

Parameters

Parameter

Description

Value

id

Specifies the ID of a clock source.

The value is an integer that ranges from 0 to 15.

By default, the ID of a clock source is 0.

source source

Specifies the clock source.

source specifies the number of a clock source.

The value is an integer that ranges from 0 to 8. The mappings between the clock source numbers and clock sources are as follows:
  • 0: Inner Clock, that is, the clock generated by the local oscillator, which cannot be changed
  • 1: BITS0, that is, the BITS0 clock
  • 2: BITS1, that is, the BITS1 clock
  • 3: Slave Board BITS0, that is, the BITS0 clock on the slave board
  • 4: Slave Board BITS1, that is, the BITS1 clock on the slave board
  • 5: Left Frame Clock, that is, the clock signal sent from the left side of the frame
  • 6: Right Frame Clock, that is, the clock signal sent from the right side of the frame
  • 7: FSU, that is, the clock on the FSU
  • 8: Slave Board FSU, that is, the clock on the peer FSU

Views

System view

Default Level

2: Configuration level

Usage Guidelines

The clock id command is used to prevent timing loops on a ring network consisting of multiple devices. The ID of the clock source can be used only in extended mode where the SSM quality level is used in clock source selection. If the system selects a clock source, the higher four bits of the S1 byte sent by the system are occupied by the ID of the clock source.

  • When the local device receives the S1 byte with the ID of its own clock source, it indicates that the device receives the clock source of its own. That is, a timing loop occurs. Then the quality level of the received clock source is set to DNU so that it is not involved in clock source selection. In this manner, timing loops are prevented.
  • If the local device receives an S1 byte without the ID of the clock source, it indicates that the clock source is from another device and can be used as the reference clock source. The S1 byte is then transmitted among devices to select the clock source.

The ID of the clock source occupies only four bits; therefore, only 16 IDs can be represented: 0-15. If multiple ring networks exist, there are not sufficient IDs for them.

To solve the problem of insufficient IDs, you can specify an ID that is not used on the local ring network for the clock sources on another ring network on the intersection point of the two ring networks. In this manner, IDs of different ring networks are isolated, and the same ID can be used by different networks.

NOTE:

The ID of the clock source is used to prevent timing loops. If a ring network consists of the device and other types of devices, it is recommended that you set the ID only for the inner clock generated by the crystal oscillator because the clocks of the device and another type of device may not match.

Example

# Set the ID of the clock source.

<HUAWEI> system-view
[HUAWEI] clock id  1 source 1

# Display IDs of clock sources.

<HUAWEI> display clock source
Reference Clock Source        Signal Fail    S1 Byte     ID       SSM
---------------------------------------------------------------------
0         Inner Clock         No             --          -        SEC
1         BITS0               Yes            --          1        DNU
2         BITS1               Yes            --          -        DNU
3         Slave Board BITS0    Yes            --          -        DNU
4         Slave Board BITS1    Yes            --          -        DNU
5         Left Frame Clock    Yes            --          -        DNU
6         Right Frame Clock   Yes            --          -        DNU
7         FSU                 Yes            --          -        DNU
8         Slave Board FSU      Yes            --          -        DNU
9         System Clock        No             --          -        SEC 

# Delete the ID of the clock source.

<HUAWEI> system-view
[HUAWEI] undo clock id source 1
[HUAWEI] display clock source
Reference Clock Source        Signal Fail    S1 Byte     ID       SSM           
---------------------------------------------------------------------           
0         Inner Clock         No             --          -        SEC           
1         BITS0               Yes            --          -        DNU           
2         BITS1               Yes            --          -        DNU           
3         Slave Board BITS0   Yes            --          -        DNU           
4         Slave Board BITS1   Yes            --          -        DNU           
5         Left Frame Clock    Yes            --          -        DNU           
6         Right Frame Clock   Yes            --          -        DNU           
7         FSU                 Yes            --          -        DNU           
8         Slave Board FSU     Yes            --          -        DNU           
9         System Clock        No             --          -        SEC           

clock left-frame | right-frame

Function

Using the clock left-frame command, you can set the priority of the clock source that an interface sends from the left side of the frame.

Using the undo clock left-frame command, you can restore the default priority of the clock source that an interface sends from the left side of the frame.

Using the clock right-frame command, you can set the priority of the clock source that an interface sends from the right side of the frame.

Using the undo clock right-frame command, you can restore the default priority of the clock source that an interface sends from the right side of the frame.

By default, the priority of a clock source is 255.

Format

clock { left-frame | right-frame } priority

undo clock { left-frame | right-frame } [ priority ]

Parameters

Parameter

Description

Value

priority

Specifies the priority of the clock source that an interface sends to the clock board.

The value is an integer that ranges from 0 to 253. The default priority of the clock source sent by an interface is 255.

Views

GE interface view, XGE interface view, 40GE interface view, 100GE interface view

Default Level

2: Configuration level

Usage Guidelines

GE electrical interfaces do not support clock syntonization.

Table 3-86 shows the boards where the clock left-frame and clock right-frame commands are used.

Table 3-86  Boards where the clock left-frame and clock right-frame commands are used

Device Type

Slot ID

Command

S7703, S9703

1-3

clock left-frame

S7706, S9706

1-3

clock left-frame

4-6

clock right-frame

S7712, S9712

1-6

clock left-frame

7-12

clock right-frame

The LPUs in each half of the frame select a line clock source to send to the main control board according to the priorities of clock sources of interfaces. If the SSM quality level is used in clock source selection, the LPUs select the clock source of the highest quality level. Otherwise, the LPUs select the qualified clock source with the highest priority.

By default, the priorities of clock sources sent from all interfaces are 255 (DIS). That is, no interface sends the clock source to the main control board. You can set priorities of clock sources on multiple interfaces by running the clock left-frame or clock right-frame command in the corresponding interface views.

NOTE:

Before running this command on the X1Eseries cards, run the set service-mode command to set the working mode of the cards to the enhanced mode.

Example

# Set the priority of the clock source that GigabitEthernet 1/0/1 sends from the left side of the frame to 20.

<HUAWEI> system-view
[HUAWEI] interface GigabitEthernet 1/0/1
[HUAWEI-GigabitEthernet1/0/1] clock left-frame 20
[HUAWEI-GigabitEthernet1/0/1] quit
[HUAWEI] display clock left-frame
Interface                     Priority            Clock Signal Selected
---------------------------------------------------------------------
GigabitEthernet1/0/1          20                  N      

clock lockout

Function

The clock lockout command locks a clock source to disable it from participating in clock source selection.

The undo clock lockout command unlocks a clock source to enable it to participate in clock source selection.

By default, all clock sources participate in clock source selection.

Format

clock lockout source source { system | bits0 | bits1 }

undo clock lockout source source { system | bits0 | bits1 }

Parameters

Parameter

Description

Value

source source

Specifies the clock source.

source specifies the number of a clock source.

The value is an integer that ranges from 0 to 8 for the clock source of the system clock and 5 to 9 for the clock source of the BITS clock.

The mappings between the clock source numbers and clock sources are as follows:

  • 0: Inner Clock, that is, the clock generated by the local oscillator, which cannot be changed
  • 1: BITS0, that is, the BITS0 clock
  • 2: BITS1, that is, the BITS1 clock
  • 3: Slave Board BITS0, that is, the BITS0 clock on the slave board
  • 4: Slave Board BITS1, that is, the BITS1 clock on the slave board
  • 5: Left Frame Clock, that is, the clock signal sent from the left side of the frame
  • 6: Right Frame Clock, that is, the clock signal sent from the right side of the frame
  • 7: FSU, that is, the clock on the FSU
  • 8: Slave Board FSU, that is, the clock on the peer FSU
  • 9: System Clock, that is, the clock selected automatically or specified by forcible switchover or manual switchover

system

Locks a clock source of the system clock.

-

bits0

Locks a clock source of the BITS0 clock.

-

bits1

Locks a clock source of the BITS1 clock.

-

Views

System view

Default Level

2: Configuration level

Usage Guidelines

Clock source 0 (inner clock) and clock source 9 (system clock) cannot be locked.

If you run the undo clock priority command to delete the priority of a clock source, the locking state of the clock source is cancelled.

Locking a clock source fails in any of the following conditions:

  • The number of the clock source to be locked for the system clock is out of the range 0-8.

  • The number of the clock source to be locked for the BITS clock is out of the range 5-9.

  • The clock source to be locked is the inner clock or system clock.

  • The priority of the clock source to be locked is not set and the clock source uses the default priority 255.

Example

# Lock the clock source sent from the left side of the frame (clock source 5).

<HUAWEI> system-view
[HUAWEI] clock lockout source 5 system

# Check whether any clock source is locked.

<HUAWEI> display clock lockout
Reference Clock Source        System         Bits0          Bits1
-----------------------------------------------------------------
0         Inner Clock         No             -              -
1         BITS0               No             -              -
2         BITS1               No             -              -
3         Slave Board BITS0    No             -              -
4         Slave Board BITS1    No             -              -
5         Left Frame Clock    Yes            No             No
6         Right Frame Clock   No             No             No
7         FSU                 No             No             No
8         Slave Board FSU      No             No             No
9         System Clock        -              No             No

# Unlock clock source 5.

<HUAWEI> system-view
[HUAWEI] undo clock lockout source 5 system
Related Topics

clock manual-switch

Function

The clock manual-switch command enables manual switchover of the clock source.

The undo clock manual-switch command cancels the manual switchover of the clock source.

By default, the system selects the clock source automatically.

Format

clock manual-switch source source { system | bits0 | bits1 }

undo clock manual-switch source source { system | bits0 | bits1 }

Parameters

Parameter

Description

Value

source source

Specifies the clock source.

source specifies the number of a clock source.

The value is an integer that ranges from 0 to 8 for the clock source of the system clock and 5 to 9 for the clock source of the BITS clock.

The mappings between the clock source numbers and clock sources are as follows:

  • 0: Inner Clock, that is, the clock generated by the local oscillator, which cannot be changed
  • 1: BITS0, that is, the BITS0 clock
  • 2: BITS1, that is, the BITS1 clock
  • 3: Slave Board BITS0, that is, the BITS0 clock on the slave board
  • 4: Slave Board BITS1, that is, the BITS1 clock on the slave board
  • 5: Left Frame Clock, that is, the clock signal sent from the left side of the frame
  • 6: Right Frame Clock, that is, the clock signal sent from the right side of the frame
  • 7: FSU, that is, the clock on the FSU
  • 8: Slave Board FSU, that is, the clock on the peer FSU
  • 9: System Clock, that is, the clock selected automatically or specified by forcible switchover or manual switchover

system

Indicates the clock source of the system clock.

-

bits0

Indicates the clock source of the BITS0 clock.

-

bits1

Indicates the clock source of the BITS1 clock.

-

Views

System view

Default Level

2: Configuration level

Usage Guidelines

The clock source can be selected in automatic, manual, or forcible mode. In automatic mode, the system selects the clock source depending on whether the SSM quality level is used in the selection.

In manual mode, you can change the clock source regardless of the priority of the clock source.

NOTE:

Manual switchover of the clock source fails in any of the following conditions:

  • The signal of the new clock source is invalid.

  • The priority of the specified clock source is set to DIS (255) by the undo clock priority command.

  • The specified clock source is locked by the clock lockout command.

  • The number of the source clock of the system clock ranges from 0 to 8.

  • The number of the source clock of the BITS clock ranges from 5 to 9.

  • The quality level of the specified clock source is equal to or lower than DNU.

  • The quality level of the specified clock source is lower than that of the original clock source when the SSM quality level is used in clock source selection.

If you run the clock force-switch command, the clock source selection mode changes from manual switchover to forcible switchover.

If you run the clock clear-switch command, the clock source selection mode changes from manual switchover to automatic mode.

Example

# Manually change the clock source of the BITS0 clock to clock source 9.

[HUAWEI] clock manual-switch source 9 bits0
[HUAWEI] display clock mode
QL-Enable  : No.
Freq-Check : No.
Retrieve   : Yes.
Hold Type  : Hold 24 hours.
Run Mode   : Trace.
Bits0      : Locked.
Bits1      : Locked.
System mode: Auto select clock source 0: Inner Clock.
Bits0 mode : Manual-switch clock source 9: System Clock.
Bits1 mode : Auto select clock source 9: System Clock.
Clock time : Free-run

# Manually change the clock source of the BITS0 clock to clock source 8, which is locked.

[HUAWEI] clock manual-switch source 8 bits0
clock-source #8 is Locked Out! cannot switch! 

clock no-retrieve

Function

Using the clock no-retrieve command, you can disable the retrieve mode of the clock source.

Using the undo clock no-retrieve command, you can enable the retrieve mode of the clock source.

By default, the clock module works in retrieve mode. That is, if a better clock source is found, the system selects this clock source automatically.

Format

clock no-retrieve

undo clock no-retrieve

Parameters

None

Views

System view

Default Level

2: Configuration level

Usage Guidelines

In non-retrieve mode, the system does not change the clock source until the original clock source fails.

You can run the display clock mode command to query the configuration result.

Example

# Disable the retrieve mode of the clock source.

<HUAWEI> system-view
[HUAWEI] clock no-retrieve

# Display information about the clock module.

<HUAWEI> display clock mode
QL-Enable  : No.
Freq-Check : No.
Retrieve   : No.
Hold Type  : Hold for ever.
Run Mode   : Free.
Bits0      : Locked.
Bits1      : Locked.
System mode: Auto select clock source 0: Inner Clock.
Bits0 mode : Auto select clock source 9: System Clock.
Bits1 mode : Auto select clock source 9: System Clock.
Clock time : Free-run 

# Enable the retrieve mode of the clock source.

<HUAWEI> system-view
[HUAWEI] undo clock no-retrieve
[HUAWEI] display clock mode
QL-Enable  : No.
Freq-Check : No.
Retrieve   : Yes.
Hold Type  : Hold for ever.
Run Mode   : Free.
Bits0      : Locked.
Bits1      : Locked.
System mode: Auto select clock source 0: Inner Clock.
Bits0 mode : Auto select clock source 9: System Clock.
Bits1 mode : Auto select clock source 9: System Clock.
Clock time : Free-run 
Related Topics

clock no-id-out (System view)

Function

Using the clock no-id-out command, you can disable a clock from sending the clock source ID.

Using the undo clock no-id-out command, you can enable a clock to send the clock source ID.

By default, a clock sends the clock source ID.

Format

clock no-id-out { bits0 | bits1 }

undo clock no-id-out { bits0 | bits1 }

Parameters

Parameter

Description

Value

bits0

Indicates the first BITS clock, BITS0.

-

bits1

Indicates the second BITS clock, BITS1.

-

Views

System view

Default Level

2: Configuration level

Usage Guidelines

After you run the clock no-id-out command, the higher four bits of the S1 byte are set to 0 when the extended SSM mode is used.

You can run the display clock command to query the configuration result.

Example

# Disable the BITS0 clock to send the clock source ID.

<HUAWEI> system-view
[HUAWEI] clock no-id-out bits0

# Display information about the BITS0 clock.

<HUAWEI> display clock bits0
Type: 2M bps.
Recv sa-bit: SA4.
Send sa-bit: SA4.
Recv s1 byte: 0x0f.
Send s1 byte: 0x0f.
Force out s1: No
ID out: No        

# Enable the BITS0 clock to send the clock source ID.

<HUAWEI> system-view
[HUAWEI] undo clock no-id-out bits0
[HUAWEI] display clock bits0
Type: 2M bps.
Recv sa-bit: SA4.
Send sa-bit: SA4.
Recv s1 byte: 0x0f.
Send s1 byte: 0x0f.
Force out s1: No
ID out: Yes    
Related Topics

clock no-id-out (interface view)

Function

Using the clock no-id-out command, you can disable an interface from sending the clock source ID.

Using the undo clock no-id-out command, you can enable an interface to send the clock source ID.

By default, an interface sends the clock source ID.

Format

clock no-id-out

undo clock no-id-out

Parameters

None

Views

GE interface view, XGE interface view, 40GE interface view, 100GE interface view

Default Level

2: Configuration level

Usage Guidelines

After you run the clock no-id-out command, the higher four bits of the S1 byte are set to 0 when the extended SSM mode is used.

You can run the display clock state command to query the configuration result.

NOTE:

This command is invalid on a GE electrical interface.

Example

# Disable GigabitEthernet1/0/0 from sending the clock source ID.

<HUAWEI> system-view
[HUAWEI] interface gigabitethernet 1/0/0
[HUAWEI-GigabitEthernet1/0/0] clock no-id-out

# Display the clock information on GigabitEthernet1/0/0.

<HUAWEI> display clock state interface gigabitethernet 1/0/0
Priority: 255.
Send S1: 02, Send SSM: PRC.
Force Out S1: Yes, The s1 byte is: 0x12.
Id-out: No.             

# Enable GigabitEthernet1/0/0 to send the clock source ID.

<HUAWEI> system-view
[HUAWEI] interface gigabitethernet 1/0/0
[HUAWEI-GigabitEthernet1/0/0] undo clock no-id-out
[HUAWEI-GigabitEthernet1/0/0] display clock state interface gigabitethernet 1/0/0
Priority: 255.
Send S1: 12, Send SSM: PRC.
Force Out S1: Yes, The s1 byte is: 0x12.
Id-out: Yes.             
Related Topics

clock priority

Function

Using the clock priority command, you can set the priority of a clock source.

Using the undo clock priority command, you can restore the default priority of a clock source.

By default, the priority of a clock source is 255.

Format

clock priority priority source source { system | bits0 | bits1 }

undo clock priority [ priority ] source source { system | bits0 | bits1 }

Parameters

Parameter

Description

Value

priority priority

Sets the priority of a clock source.

The value is an integer that ranges from 0 to 253.

By default, the priority of the inner clock source and system clock source is 254, and the priority of other clock sources is 255.

source source

Specifies the clock source.

source specifies the number of a clock source.

The value is an integer that ranges from 0 to 9.

The number of the clock source for the system clock ranges from 0 to 8.

The number of the clock source for the BITS clocks ranges from 5 to 9.

The mappings between the clock source numbers and clock sources are as follows:

  • 0: Inner Clock, that is, the clock generated by the local oscillator, which cannot be changed
  • 1: BITS0, that is, the BITS0 clock
  • 2: BITS1, that is, the BITS1 clock
  • 3: Slave Board BITS0, that is, the BITS0 clock on the slave board
  • 4: Slave Board BITS1, that is, the BITS1 clock on the slave board
  • 5: Left Frame Clock, that is, the clock signal sent from the left side of the frame
  • 6: Right Frame Clock, that is, the clock signal sent from the right side of the frame
  • 7: FSU, that is, the clock on the FSU
  • 8: Slave Board FSU, that is, the clock on the peer FSU
  • 9: System Clock, that is, the clock selected automatically or specified by forcible switchover or manual switchover

system

Indicates the clock source of the system clock.

-

bits0

Indicates the clock source of the BITS0 clock.

-

bits1

Indicates the clock source of the BITS1 clock.

-

Views

System view

Default Level

2: Configuration level

Usage Guidelines

If the priority of a clock source is 255 (DIS), the clock source does not participate in clock source selection.

A smaller priority value indicates a higher priority.

If the SSM quality level is used in clock source selection, the SSM quality levels of clock sources are compared first, and then their priorities are compared.

Example

# Set the priority of clock source 1 to 11.

<HUAWEI> system-view
[HUAWEI] clock priority 11 source 1 system

# Display priorities of clock sources.

<HUAWEI> display clock priority
Reference Clock Source        System         bits0          bits1
-----------------------------------------------------------------
0         Inner Clock         254            -              -
1         BITS0               11             -              -
2         BITS1               255            -              -
3         Slave Board BITS0    255            -              -
4         Slave Board BITS1    255            -              -
5         Left Frame Clock    255            255            255
6         Right Frame Clock   255            255            255
7         FSU                 255            255            255
8         Slave Board FSU      255            255            255
9         System Clock        -              254            254

clock ql-enable

Function

Using the clock ql-enable command, you can enable the system to use the SSM quality level for clock source selection.

Using the undo clock ql-enable command, you can disable the system from using the SSM quality level for clock source selection.

By default, the SSM quality level is not used in clock source selection.

Format

clock ql-enable [ extend ]

undo clock ql-enable [ extend ]

Parameters

Parameter

Description

Value

extend

Indicates the extended SSM mode in which the clock source ID can be sent in the four higher bits of the S1 byte in the SSM message.

-

Views

System view

Default Level

2: Configuration level

Usage Guidelines

NOTE:

If the SSM quality level of a clock source cannot be obtained, you can run the clock ssm-config command to specify an SSM quality level for the clock source.

If the SSM quality level is used in clock source selection, the system first compares the quality level of clock sources, and then compares their priorities. If the SSM quality is not used in clock source selection, the system selects the clock source according to the priorities of clock sources.

In extended SSM mode, the higher four bits of the S1 bytes are used to transmit the clock source ID, which reduces timing loops on the network.

Example

# Enable the system to use the SSM quality level for clock source selection.

<HUAWEI> system-view
[HUAWEI] clock ql-enable
[HUAWEI] display clock mode
QL-Enable  : Yes.
Freq-Check : Yes.
Retrieve   : Yes.
Hold Type  : Hold for ever.
Run Mode   : Free.
Bits0      : Locked.
Bits1      : Locked.
System mode: Auto select clock source 0: Inner Clock.
Bits0 mode : Auto select clock source 9: System Clock.
Bits1 mode : Auto select clock source 9: System Clock.
Clock time : Free-run         
Related Topics

clock ql-unknown

Function

Using the clock ql-unknown command, you can set the unknown quality level.

Using the undo clock ql-unknown command, you can restore the default unknown quality level.

By default, the unknown quality level is Do Not Use (DNU).

Format

clock ql-unknown { prc | ssu-t | ssu-l | sec }

undo clock ql-unknown [ prc | ssu-t | ssu-l | sec ]

Parameters

Parameter

Description

Value

prc

Configures the clock source with the unknown SSM quality level as the stratum-1 clock, that is, the master reference clock.

-

ssu-t

Configures the clock source with the unknown SSM quality level as the stratum-2 clock.

-

ssu-l

Configures the clock source with the unknown SSM quality level as the stratum-3 clock.

-

sec

Configures the clock source with the unknown SSM quality level as the SDH clock.

-

Views

System view

Default Level

2: Configuration level

Usage Guidelines

The clock ql-unknown command is used to set the SSM quality level of all-0 SSM messages.

If you run the command repeatedly, the latest configuration takes effect.

The unknown SSM quality level can be used in clock source selection only after you run the clock ql-enable command to enable the system to use the SSM quality level for clock source selection.

When receiving an all-0 SSM message, the system parses the SSM quality level of the clock source as the unknown level.

Example

# Configure a clock source of the unknown quality level as the SDH clock.

<HUAWEI> system-view
[HUAWEI] clock ql-unknown sec
[HUAWEI] display clock ql-unknown
Clock unknown QL: SEC
[HUAWEI] undo clock ql-unknown
[HUAWEI] display clock ql-unknown
Clock unknown QL: DNU

clock recv-sa-bit | clock send-sa-bit

Function

The clock recv-sa-bit command specifies the SA bit field from which the SDH synchronization information code (S1 byte) is received.

The undo clock recv-sa-bit command restores the default setting that the S1 byte is received by the SA4 bit field.

The clock send-sa-bit command specifies the SA bit field that is used to send the S1 byte.

The undo clock send-sa-bit command restores the default setting that the S1 byte is sent by the SA4 bit field.

By default, the S1 byte is transmitted in the SA4 bit field.

Format

clock recv-sa-bit { sa4 | sa5 | sa6 | sa7 | sa8 } { bits0 | bits1 }

undo clock recv-sa-bit { sa4 | sa5 | sa6 | sa7 | sa8 } { bits0 | bits1 }

clock send-sa-bit { sa4 | sa5 | sa6 | sa7 | sa8 } { bits0 | bits1 }

undo clock send-sa-bit { sa4 | sa5 | sa6 | sa7 | sa8 } { bits0 | bits1 }

Parameters

Parameter

Description

Value

sa4

Uses the SA4 bit field to transmit the S1 byte.

-

sa5

Uses the SA5 bit field to transmit the S1 byte.

-

sa6

Uses the SA6 bit field to transmit the S1 byte.

-

sa7

Uses the SA7 bit field to transmit the S1 byte.

-

sa8

Uses the SA8 bit field to transmit the S1 byte.

-

bits0

Indicates the first BITS clock, BITS0.

-

bits1

Indicates the second BITS clock, BITS1.

-

Views

System view

Default Level

2: Configuration level

Usage Guidelines

A multiframe transmitted between BITS interfaces consists of eight sub-multiframes. Each frame contains five spare bits: SA4 bit to SA8 bit. You can select any one of the spare SA bits to transmit the SDH synchronization code (S1 byte). The eight frames jointly carry the eight bits of the S1 byte.

If sender and receiver are both Ethernet clock synchronization devices, you do not need to run the clock recv-sa-bit or clock send-sa-bit command because the Ethernet clock synchronization devices can identify the S1 byte no matter which bit transmits it. The commands are used when an Ethernet clock synchronization device synchronizes the clock with another type of device through the BITS interface. In this case, you need to specify the same bit that transmits the S1 byte on both ends to ensure that both ends can identify the S1 byte.

Example

# Configure the BITS0 clock to receive the S1 byte from the SA5 bit field.

<HUAWEI> system-view
[HUAWEI] clock recv-sa-bit sa5 bits0

# Configure the BITS0 clock to send the S1 byte by using the SA8 bit field.

<HUAWEI> system-view
[HUAWEI] clock send-sa-bit sa8 bits0

# Display the mode of the BITS0 clock.

<HUAWEI> display clock bits0
Direction: out.
Type: 1pps.
Recv sa-bit: SA5.
Send sa-bit: SA8.
Force out s1: No
ID out: Yes
Related Topics

clock ssm-config

Function

The clock ssm-config command sets the SSM quality level of a clock source.

The undo clock ssm-config command restores the default SSM quality level of a clock source.

By default, the SSM quality level of a clock source is SEC.

Format

clock ssm-config { prc | ssu-t | ssu-l | sec | dnu } source source

undo clock ssm-config [ prc | ssu-t | ssu-l | sec | dnu ] source source

Parameters

Parameter

Description

Value

prc

Indicates the stratum-1 clock, that is, the master reference clock.

-

ssu-t

Indicates the stratum-2 clock.

-

ssu-l

Indicates the stratum-3 clock.

-

sec

Indicates the SDH clock.

-

dnu

Indicates that the clock cannot be used for synchronization.

-

source source

Specifies the clock source.

source specifies the number of a clock source.

The value is an integer that ranges from 0 to 8.

The mappings between the clock source numbers and clock sources are as follows:

  • 0: Inner Clock, that is, the clock generated by the local oscillator, which cannot be changed
  • 1: BITS0, that is, the BITS0 clock
  • 2: BITS1, that is, the BITS1 clock
  • 3: Slave Board BITS0, that is, the BITS0 clock on the slave board
  • 4: Slave Board BITS1, that is, the BITS1 clock on the slave board
  • 5: Left Frame Clock, that is, the clock signal sent from the left side of the frame
  • 6: Right Frame Clock, that is, the clock signal sent from the right side of the frame
  • 7: FSU, that is, the clock on the FSU
  • 8: Slave Board FSU, that is, the clock on the peer FSU

Views

System view

Default Level

2: Configuration level

Usage Guidelines

The default SSM quality level of the inner clock source and system clock (19.44 MHz) is sec.

The SSM quality level of the system clock will change to the SSM quality level of the clock source selected by the system.

NOTE:

At least one clock source should be available in any situation; therefore, do not set the SSM quality level of the inner clock source to DNU.

Example

# Set the SSM quality level of the inner clock source to DNU.

<HUAWEI> system-view
[HUAWEI] clock ssm-config dnu source 0
Cannot set Inner clock QL to DNU.

# Set the SSM quality level of clock source 1 to prc.

<HUAWEI> system-view
[HUAWEI] clock ssm-config prc source 1

# Display the SSM quality levels of clock sources.

<HUAWEI> display clock ssm-config
Reference      Clock Source                  SSM Config
-----------------------------------------------------------------
0              Inner Clock                   ---
1              BITS0                         PRC
2              BITS1                         ---
3              Slave Board BITS0              ---
4              Slave Board BITS1              ---
5              Left Frame Clock              ---
6              Right Frame Clock             ---
7              FSU                           ---
8              Slave Board FSU                ---

# Cancel the setting of the SSM quality level of clock source 1.

<HUAWEI> system-view
[HUAWEI]undo clock ssm-config source 1
[HUAWEI]display clock ssm-config
Reference      Clock Source                  SSM Config                         
---------------------------------------------------------------------           
0              Inner Clock                   ---                                
1              BITS0                         ---                                
2              BITS1                         ---                                
3              Slave Board BITS0             ---                                
4              Slave Board BITS1             ---                                
5              Left Frame Clock              ---                                
6              Right Frame Clock             ---                                
7              FSU                           ---                                
8              Slave Board FSU               ---                 

clock wait-to-restore

Function

The clock wait-to-restore command sets the wait to restore (WTR) time of a clock source.

The undo clock wait-to-restore command restores the WTR time of a clock source.

By default, the WTR time of a clock source is 1 minute.

Format

clock wait-to-restore wait-to-restore-time source source

undo clock wait-to-restore [ wait-to-restore-time ] source source

Parameters

Parameter

Description

Value

wait-to-restore-time

Specifies the WTR time of a clock source.

The value is an integer that ranges from 0 to 12. The unit is minute.

The default value is 1 minute.

source source

Specifies the clock source.

source specifies the number of a clock source.

The value is an integer that ranges from 0 to 8.

The mappings between the clock source numbers and clock sources are as follows:

  • 0: Inner Clock, that is, the clock generated by the local oscillator, which cannot be changed
  • 1: BITS0, that is, the BITS0 clock
  • 2: BITS1, that is, the BITS1 clock
  • 3: Slave Board BITS0, that is, the BITS0 clock on the slave board
  • 4: Slave Board BITS1, that is, the BITS1 clock on the slave board
  • 5: Left Frame Clock, that is, the clock signal sent from the left side of the frame
  • 6: Right Frame Clock, that is, the clock signal sent from the right side of the frame
  • 7: FSU, that is, the clock on the FSU
  • 8: Slave Board FSU, that is, clock on the peer FSU
NOTE:

This command sets the WTR for the clock sources 0 to 8. For example, if source is set to 5, the command sets the WTR time for the Left Frame Clock. The WTR time does not take effect for clock switching between ports in the same half frame. In application, if multiple clock sources exist, they should be distributed in different half frames.

Views

System view

Default Level

2: Configuration level

Usage Guidelines

When a lost clock source is restored, the system waits for a period of 0 to 12 minutes before considering the clock source available. During this period, the system considers the clock source lost.

Setting the delay time can avoid some mistakes in determining the clock source caused by occasional signal jitter on the network.

The default WTR time of a clock source is 1 minute. Generally, you do not need to change the default value. If you want to see the clock source switching result during debugging, set the WTR time to 0.

Example

# Set the WTR time of clock source 1.

<HUAWEI> system-view
[HUAWEI] clock wait-to-restore 0 source 1

# Display the WTR time of clock sources.

<HUAWEI> display clock wait-to-restore
Reference      Clock Source                  WTR(unit:minute)
-----------------------------------------------------------------
0              Inner Clock                   1
1              BITS0                         0
2              BITS1                         1
3              Slave Board BITS0             1
4              Slave Board BITS1             1
5              Left Frame Clock              0
6              Right Frame Clock             1
7              FSU                           1
8              Slave Board FSU               1

# Cancel the setting of WTR time of clock source 1.

<HUAWEI> system-view
[HUAWEI] undo clock wait-to-restore source 1
[HUAWEI] display clock wait-to-restore
Reference      Clock Source                  WTR(unit:minute)                   
---------------------------------------------------------------------           
0              Inner Clock                   1                                  
1              BITS0                         1                                  
2              BITS1                         1                                  
3              Slave Board BITS0             1                                  
4              Slave Board BITS1             1                                  
5              Left Frame Clock              0                                  
6              Right Frame Clock             1                                  
7              FSU                           1                                  
8              Slave Board FSU               1                     

display clock

Function

Using the display clock command, you can view the configuration of a BITS clock.

Format

display clock { bits0 | bits1 } [ slave ]

Parameters

Parameter

Description

Value

bits0

Indicates the BITS0 clock on the master clock board.

-

bits1

Indicates the BITS1 clock on the master clock board.

-

slave

Indicates a BITS clock on the slave clock board.

-

Views

All views

Default Level

1: Monitoring level

Usage Guidelines

After you run the clock bits-type, clock recv-sa-bit | clock send-sa-bit, or clock force-out-s1 (System view) command and so on to configure a BITS clock, you can run the display clock command to check the configuration result.

Example

# Display information about the BITS0 clock.

<HUAWEI> display clock bits0
Direction: out.
Type: 1pps.
Recv sa-bit: SA5.
Send sa-bit: SA8.
Force out s1: Yes, The s1 byte configed is:0x11.
ID out: Yes

# Display information about the BITS1 clock.

<HUAWEI> display clock bits1
Type: 2M bps.
Recv sa-bit: SA4.
Send sa-bit: SA4.
Recv s1 byte: 0x0f.
Send s1 byte: 0x12.
Force out s1: No
ID out: Yes       
Table 3-87  Description of the display clock command output

Item

Description

Direction

Transmission direction of the BITS clock signal, which can be in or out. If the BITS clock works in clock syntonization mode, namely, 2 Mbps, 1.544 Mbps, or 2 MHz mode, this field is meaningless.

Type

Mode of the BITS clock.

Recv sa-bit

SA bit from which the S1 byte is received.

Send sa-bit

SA bit through which the S1 byte is sent.

Recv s1-bit

Value of the S1 byte received from the LPU.

Send s1-bit

Value of the S1 byte sent by the BITS clock. The value can be obtained from the SSM quality level of the clock source selected by the BITS clock or set by the clock send-sa-bit command.

Force out s1

S1 byte that is set forcibly.

ID out

Whether the ID of the BITS clock is contained in the S1 byte.

display clock description

Function

Using the display clock description command, you can view the meaning of each clock source number.

Format

display clock description

Parameters

None

Views

All views

Default Level

1: Monitoring level

Usage Guidelines

This command displays all the clock sources supported by the device.

NOTE:

Clock sources 7 and 8 are reserved and not supported by the device currently.

Example

# Display the description of clock sources.

<HUAWEI> display clock description
Reference           Clock-source                                                
---------------------------------------------------------------------           
0                   Inner Clock                                                 
1                   BITS0                                                       
2                   BITS1                                                       
3                   Slave Board BITS0                                           
4                   Slave Board BITS1                                           
5                   Left Frame Clock                                            
6                   Right Frame Clock                                           
7                   FSU                                                         
8                   Slave Board FSU                                             
9                   System Clock                                                
10                  Peer System Clock                                           
Table 3-88  Description of the display clock description command output

Item

Description

Reference

Number of a clock source.

Clock-source

Name of a clock source.

display clock freq-check-range

Function

Using the display clock freq-check-range command, you can view the valid range of clock frequency offset.

Format

display clock freq-check-range

Parameters

None

Views

All views

Default Level

1: Monitoring level

Usage Guidelines

After setting the valid range of clock frequency offset by running the clock freq-check-range command, you can run the display clock freq-check-range command to check the configuration result.

Example

# Set the valid range of frequency offset.

<HUAWEI> system-view
[HUAWEI] clock freq-check-range 50 600

# Display the valid range of frequency offset.

<HUAWEI> display clock freq-check-range
Info: Clock frequency check range: [-0.50 ppm, 6.00 ppm].

# Restore the default valid range of frequency offset.

<HUAWEI> system-view
[HUAWEI] undo clock freq-check-range
Table 3-89  Description of the display clock freq-check-range command output

Item

Description

Clock frequency check range

Valid range of clock frequency offset.

display clock freq-check-result

Function

Using the display clock freq-check-result command, you can view the check result of the clock frequency offset.

Format

display clock freq-check-result

Parameters

None

Views

All views

Default Level

1: Monitoring level

Usage Guidelines

By default, the check result of the clock frequency offset does not affect the clock source selection. After you run the clock freq-check command, the system selects the clock source according to the check result. The clock source whose frequency offset is out of the valid range is tagged "signal-fail."

NOTE:
  • The system does not check the frequency offset of the clock source that is tagged "signal-fail."
  • The system does not check the frequency of the inner clock.

Example

# Display information about clock sources.

<HUAWEI> display clock source
Reference Clock Source        Signal Fail    S1 Byte     ID       SSM
---------------------------------------------------------------------
0         Inner Clock         No             --          -        SEC
1         BITS0               Yes            --          -        DNU
2         BITS1               Yes            --          -        DNU
3         Slave Board BITS0   Yes            --          -        DNU
4         Slave Board BITS1   Yes            --          -        DNU
5         Left Frame Clock    Yes            --          -        DNU
6         Right Frame Clock   Yes            --          -        DNU
7         FSU                 Yes            --          -        DNU
8         Slave Board FSU     Yes            --          -        DNU
9         System Clock        No             --          -        SEC

# Display the check result of the clock frequency offset.

<HUAWEI> display clock freq-check-result
Reference      Clock Source                  Freq-Check-Result(Unit:ppm)        
---------------------------------------------------------------------           
0              Inner Clock                   ---                                
1              BITS0                         Unchecked                          
2              BITS1                         Unchecked                          
3              Slave Board BITS0             Unchecked                          
4              Slave Board BITS1             Unchecked                          
5              Left Frame Clock              Unchecked                          
6              Right Frame Clock             Unchecked                          
7              System Clock                  0.00                               
8              Peer System Clock             Unchecked                          
Table 3-90  Description of the display clock freq-check-result command output

Item

Description

Reference

Number of a clock source.

Clock-source

Name of a clock source.

Signal Fail

Whether the signal of a clock source is invalid.

S1 Byte

Value of the S1 byte.

ID

ID of a clock source.

SSM

SSM quality level of a clock source.

Freq-Check-Result(Unit:ppm)

Check result of the clock frequency offset.

display clock hard-state

Function

Using the display clock hard-state command, you can view information about the hardware of the clock board, including the version and running status of the hardware.

Format

display clock hard-state [ slave ]

Parameters

Parameter

Description

Value

slave

Indicates the slave main control board.

-

Views

All views

Default Level

1: Monitoring level

Usage Guidelines

By using this command, you can check whether the board works normally.

Example

# Display information about the hardware of the clock board.

<HUAWEI> display clock hard-state
E1/T1 Framer Version  : 20
Clock Chip Version    : 21
FPGA Logic Version    : 201
FPGA Create Time      : 2009/04/16, 15:00
1588 Logic Version    : 16
DSP CBB Version       : 1.40T03
FPGA State            : Normal
DSP State             : Normal
E1/T1 Framer State    : Normal
Clock Chip State      : Normal  
Table 3-91  Description of the display clock hard-state command output

Item

Description

E1/T1 Framer Version

Version of the E1/T1 framer.

Clock Chip Version

Version of the clock chip.

FPGA Logic Version

Logical version of the field programmable gate array (FPGA).

FPGA Create Time

Time when the FPGA is created.

1588 Logic Version

Logical version of the 1588 clock.

DSP CBB Version

Version of the digital signal processing common building block (DPS CBB).

FPGA state

State of the FPGA.

DSP state

State of the DSP.

E1/T1 Framer State

State of the E1/T1 framer.

Clock Chip State

State of the clock chip.

display clock hold-off-time

Function

Using the display clock hold-off-time command, you can view the delay time for the system to consider a clock source lost.

Format

display clock hold-off-time

Parameters

None

Views

All views

Default Level

1: Monitoring level

Usage Guidelines

After running the clock hold-off-time command to set the delay time for the system to consider a clock source lost, you can run the display clock hold-off-time command to check the configuration result.

Example

# Set the delay time for the system to consider clock source 1 lost.

<HUAWEI> system-view
[HUAWEI] clock hold-off-time 3 source 1

# Display the delay time.

<HUAWEI> display clock hold-off-time
Reference      Clock Source                  Hold Off(unit:100ms)               
---------------------------------------------------------------------           
0              Inner Clock                   5                                  
1              BITS0                         3                                  
2              BITS1                         5                                  
3              Slave Board BITS0             5                                  
4              Slave Board BITS1             5                                  
5              Left Frame Clock              5                                  
6              Right Frame Clock             5                                  
Table 3-92  Description of the display clock hold-off-time command output

Item

Description

Reference

Number of a clock source.

Clock Source

Name of a clock source.

Hold Off (unit:100ms)

Delay time for the system to consider a clock source lost.

Related Topics

display clock mode

Function

Using the display clock mode command, you can view the working mode of the clock source. By viewing the displayed information, you can check whether the SSM quality level is used in clock source selection, whether the check result of the clock frequency offset affects clock source selection, and whether the clock mode works in retrieve mode, and so on.

Format

display clock mode [ slave ]

Parameters

Parameter

Description

Value

slave

Indicates the slave main control board.

-

Views

All views

Default Level

1: Monitoring level

Usage Guidelines

This command displays the clock information, including whether the SSM quality level is used in clock source selection, whether the check result of the clock frequency offset affects clock source selection, clock holding mode, and status of the clock.

Example

# Display information about the clock module.

<HUAWEI> display clock mode
QL-Enable  : No.
Freq-Check : No.
Retrieve   : Yes.
Hold Type  : Hold 24 hours.
Run Mode   : Free.
Bits0      : Locked.
Bits1      : Locked.
System mode: Auto select clock source 0: Inner Clock.
Bits0 mode : Auto select clock source 9: System Clock.
Bits1 mode : Auto select clock source 9: System Clock.
Clock time : Free-run

Table 3-93  Description of the display clock mode command output

Item

Description

QL-Enable

Whether the SSM quality level is used in clock source selection.

Freq-Check

Whether the check result of the clock frequency offset affects clock source selection.

Retrieve

Whether a better clock source can replace the current clock source.

Hold Type

Whether the clock module works in permanent holding mode or 24-hour holding mode.

Run Mode

The clock chip can work in any of the following modes:
  • Tracing

    If a BITS clock or circuit clock is selected as the clock source, the clock chip needs to trace and lock the frequency of the clock. This task is performed by the PLL.

  • Holding

    When tracing an external clock (a BITS clock or circuit clock), the clock chip keeps saving the data of the clock.

    When the clock cannot be used as the clock source, the clock chip maintains the frequency of the clock source for a certain period (24 hours at most) according to the clock data saved previously.

    In permanent holding mode, the clock chip uses the last saved data as the output clock frequency.

  • Free running

    In free running mode, the clock chip uses the clock generated by the oscillator as the external clock.

Bits0

Whether the BITS0 clock is locked.

Bits1

Whether the BITS1 clock is locked.

System mode

Clock source selection mode of the system clock.

Bits0 mode

Clock source selection mode of the BITS0 clock.

Bits1 mode

Clock source selection mode of the BITS1 clock.

Clock time

Clock source of the clock board.

display clock left-frame | right-frame

Function

Using the display clock left-frame command, you can view information about an interface that sends the clock sources from the left side of the frame, including the priority of the clock source and whether the interface sends the clock source to the main control board.

Using the display clock right-frame command, you can view information about an interface that sends the clock sources from the right side of the frame, including the priority of the clock source and whether the interface sends the clock source to the main control board.

Format

display clock left-frame

display clock right-frame

Parameters

None

Views

All views

Default Level

1: Monitoring level

Usage Guidelines

After running the clock { left-frame | right-frame } command to set the priority of the clock source sent from an interface, you can run the display clock { left-frame | right-frame } command to check the configuration result.

Example

# Set the priority of the clock source that GigabitEthernet1/0/1 sends from the left side of the frame to 20. Then check the configuration result.

<HUAWEI> system-view
[HUAWEI] interface gigabitethernet 1/0/1
[HUAWEI-GigabitEthernet1/0/1] clock left-frame 20
[HUAWEI-GigabitEthernet1/0/1] quit
[HUAWEI] quit
<HUAWEI> display clock left-frame
Interface                     Priority            Clock Signal Selected
---------------------------------------------------------------------
GigabitEthernet1/0/1          20                  N      
Table 3-94  Description of the display { clock left-frame | right-frame } command output

Item

Description

Interface

Interface number.

Priority

Priority of the clock source that the interface sends to the main control board.

Clock Signal Selected

Whether the interface sends the clock source to the main control board.

display clock lockout

Function

Using the display clock lockout command, you can check whether a clock source is locked, that is, whether it is excluded from clock source selection.

Format

display clock lockout

Parameters

None

Views

All views

Default Level

1: Monitoring level

Usage Guidelines

After running the clock lockout command to exclude a clock source from clock source selection, you can run the display clock lockout command to check the configuration result.

Example

# Exclude the clock source sent from the left side of the frame (clock source 5) from clock source selection.

<HUAWEI> system-view
[HUAWEI] clock lockout source 5 system

# Check whether clock source 5 is excluded from clock source selection.

<HUAWEI> display clock lockout
Reference Clock Source        System         Bits0          Bits1               
---------------------------------------------------------------------           
0         Inner Clock         No             -              -                   
1         BITS0               No             -              -                   
2         BITS1               No             -              -                   
3         Slave Board BITS0   No             -              -                   
4         Slave Board BITS1   No             -              -                   
5         Left Frame Clock    Yes             No             No                  
6         Right Frame Clock   No             No             No                  
7         System Clock        -              No             No                  
Table 3-95  Description of the display clock lockout command output

Item

Description

Reference

Number of a clock source.

Clock-source

Name of a clock source.

System

System clock.

Bits0

BITS0 clock.

Bits1

BITS1 clock.

Related Topics

display clock priority

Function

Using the display clock priority command, you can view the priorities of clock sources.

Format

display clock priority

Parameters

None

Views

All views

Default Level

1: Monitoring level

Usage Guidelines

After running the clock priority command to set the priority of a clock source, you can run the display clock priority command to check the configuration result.

A smaller priority value indicates a higher priority.

Example

# Set the priority of clock source 1 to 11.

<HUAWEI> system
[HUAWEI] clock priority 11 source 1 system

# Display priorities of clock sources.

<HUAWEI> display clock priority
Reference Clock Source        System         bits0          bits1               
---------------------------------------------------------------------           
0         Inner Clock         254            -              -                   
1         BITS0               11             -              -                   
2         BITS1               255            -              -                   
3         Slave Board BITS0   255            -              -                   
4         Slave Board BITS1   255            -              -                   
5         Left Frame Clock    255            255            255                 
6         Right Frame Clock   255            255            255                 
7         System Clock        -              254            254                 
Table 3-96  Description of the display clock priority command output

Item

Description

Reference

Number of a clock source.

Clock-source

Name of a clock source.

System

System clock.

bits0

BITS0 clock.

bits1

BITS1 clock.

Related Topics

display clock ql-unknown

Function

Using the display clock ql-unknown command, you can view the quality level mapping the unknown quality level.

Format

display clock ql-unknown

Parameters

None

Views

All views

Default Level

1: Monitoring level

Usage Guidelines

After running the clock ql-unknown command to set the unknown quality level, you can run the display clock ql-unknown command to check the configuration result.

Example

# Configure a clock source of the unknown quality level as the SDH clock.

<HUAWEI> system-view
[HUAWEI] clock ql-unknown sec
[HUAWEI] display clock ql-unknown
Info: Clock unknown QL: SEC
[HUAWEI] undo clock ql-unknown
[HUAWEI] display clock ql-unknown
Info: Clock unknown QL: DNU
Table 3-97  Description of the display clock ql-unknown command output

Item

Description

Clock unknown QL

the unknown SSM quality level

display clock selection

Function

Using the display clock selection command, you can view the result of clock source selection.

Format

display clock selection [ slave ]

Parameters

Parameter

Description

Value

slave

Indicates the slave main control board.

-

Views

All views

Default Level

1: Monitoring level

Usage Guidelines

This command displays the clock sources selected for the system clock, BITS0 clock, and BITS1 clock.

Example

# Display the result of clock source selection.

<HUAWEI> display clock selection
Type                          Clock Source Selected
-----------------------------------------------------------------
system                        5. Left Frame Clock
bits0                         5. Left Frame Clock
bits1                         9. System Clock
Table 3-98  Description of the display clock selection command output

Item

Description

Type

Type of a clock.

Clock Source Selected

Reference clock source selected for a clock.

display clock self-test-result

Function

Using the display clock self-test-result command, you can view the startup self-check information of the clock board.

Format

display clock self-test-result [ slave ]

Parameters

Parameter

Description

Value

slave

Indicates the slave main control board.

-

Views

All views

Default Level

1: Monitoring level

Usage Guidelines

By using this command, you can view the startup self-check information of the clock board to check whether the clock board works normally.

Example

# Display the startup self-check information of the clock board.

<HUAWEI> display clock self-test-result
FPGA State             : Normal
E1/T1 Framer State     : Normal
DSP State              : Normal
Clock Chip State       : Normal
E1/T1 Framer OSC State : Normal
DSP OSC State          : Normal
Clock Chip OSC State   : Normal   
Table 3-99  Description of the display clock self-test-result command output

Item

Description

FPGA state

Status of the field programmable gate array (FPGA).

E1/T1 Framer State

Status of the E1/T1 framer.

DSP state

Status of the DSP.

Clock Chip State

Status of the clock chip.

E1/T1 Framer OSC State

Status of the Optical Supervisory Channel (OSC) of the E1/T1 framer.

DSP OSC State

Status of the OSC of the DSP.

Clock Chip OSC State

Status of the OSC of the clock chip.

display clock source

Function

Using the display clock source command, you can view information about clock sources to check the SSM quality level of each clock source and whether the signal of any clock source is invalid, and so on.

Format

display clock source

Parameters

None

Views

All views

Default Level

1: Monitoring level

Usage Guidelines

This command displays information about clock sources, including the S1 byte, clock id and SSM quality level of each clock source, and whether the signal of a clock source is invalid (signal-fail).

If the SSM quality level of a clock source can be obtained from the system automatically, the actual SSM quality level is displayed. If the SSM quality level of a clock source is set manually, for example, a BITS clock working in hz-2m mode, the manually set SSM quality level is displayed. If the SSM quality level of a clock source (except the inner clock and the system clock) cannot be obtained automatically or set manually, the SSM quality level is displayed as DNU. The SSM quality level of the inner clock and the system clock is displayed as SEC.

If you have run the clock id command to set the ID of a clock source, the display clock source command also displays the ID of the clock source. If the ID of a clock source is not set, the ID field in the output information is empty.

Example

# Display information about clock sources.

<HUAWEI> display clock source
Reference Clock Source        Signal Fail    S1 Byte     ID       SSM           
---------------------------------------------------------------------           
0         Inner Clock         No             --          -        SEC           
1         BITS0               Yes            --          -        DNU           
2         BITS1               Yes            --          -        DNU           
3         Slave Board BITS0   Yes            --          -        DNU           
4         Slave Board BITS1   Yes            --          -        DNU           
5         Left Frame Clock    Yes            --          -        DNU           
6         Right Frame Clock   Yes            --          -        DNU           
7         System Clock        No             --          -        SEC           
Table 3-100  Description of the display clock source command output

Item

Description

Reference

Number of a clock source.

Clock-source

Name of a clock source.

Signal Fail

Whether the signal of a clock source is invalid.

S1 Byte

S1 byte obtained from the circuit.

ID

ID of a clock source.

SSM

SSM quality level of a clock source.

display clock ssm-config

Function

Using the display clock ssm-config command, you can view the configured SSM quality levels of clock sources.

Format

display clock ssm-config

Parameters

None

Views

All views

Default Level

1: Monitoring level

Usage Guidelines

After running the clock ssm-config command to set the SSM quality level of a clock source, you can run the display clock ssm-config command to check the configuration result.

Example

# Set the SSM quality level of clock source 1 to prc.

<HUAWEI> system-view
[HUAWEI] clock ssm-config prc source 1

# Display the SSM quality levels of clock sources.

<HUAWEI> display clock ssm-config
Reference      Clock Source                  SSM Config                         
---------------------------------------------------------------------           
0              Inner Clock                   ---                                
1              BITS0                         ---                                
2              BITS1                         ---                                
3              Slave Board BITS0             ---                                
4              Slave Board BITS1             ---                                
5              Left Frame Clock              ---                                
6              Right Frame Clock             ---                                
7              FSU                           ---                                
8              Slave Board FSU               ---                                
Table 3-101  Description of the display clock ssm-config command output

Item

Description

Reference

Number of a clock source.

Clock-source

Name of a clock source.

SSM Config

SSM quality level of a clock source.

Related Topics

display clock state

Function

Using the display clock state command, you can view the clock status on an interface.

Format

display clock state interface interface-type interface-number

Parameters

Parameter

Description

Value

interface interface-type interface-number

Specifies the type and number of an interface.

The type of the interface can be GigabitEthernet.

The interface number is selected according to the configuration of the device.

Views

All views

Default Level

1: Monitoring level

Usage Guidelines

Normally, the clock module sets the S1 byte to be sent according to the SSM level of the clock source.

Example

# Display the clock state on an interface where the priority of the clock source is not set.

<HUAWEI> display clock state interface gigabitethernet 1/0/0
Priority: 255.                                                                  
Send S1: 0F, Send SSM: DNU.                                                     
Force Out S1: No.                                                               
Id-out: Yes.     

# Display the clock state on an interface where the priority of the clock source is set.

<HUAWEI> display clock state interface gigabitethernet 1/0/0
SF(signal fail): No.
Priority: 0.
Recv S1: 0F, Recv SSM: DNU.
Send S1: 0F, Send SSM: DNU.
Force Out S1: No.
Id-out: Yes.
Table 3-102  Description of the display clock state command output

Item

Description

SF(signal fail)

Whether the clock source can provide valid clock signals.

Priority

The priority of the clock source.

Recv S1

S1 byte received by the interface.

Recv SSM

SSM quality level of the clock signal received by the interface.

Send S1

S1 byte sent by the interface.

Send SSM

SSM quality level of the clock signal sent by the interface.

Force out s1

S1 byte that is sent forcibly. The lower four bits of the S1 byte indicate the SSM quality level, and the higher four bits of the S1 byte is the clock source ID used in extended mode.

Id-out

Whether the higher four bits of the S1 byte are used to transmit the clock source ID. If the value is no, it indicates that the higher four bits of the S1 byte are set to 0.

display clock wait-to-restore

Function

Using the display clock wait-to-restore command, you can view the WTR time of a clock source.

Format

display clock wait-to-restore

Parameters

None

Views

All views

Default Level

1: Monitoring level

Usage Guidelines

After running the clock wait-to-restore command to set the WTR time of a clock source, you can run the display clock wait-to-restore command to check the configuration result.

Example

# Display the WTR time of clock sources.

<HUAWEI> display clock wait-to-restore
Reference      Clock Source                  WTR(unit:minute)                   
---------------------------------------------------------------------           
0              Inner Clock                   1                                  
1              BITS0                         1                                  
2              BITS1                         1                                  
3              Slave Board BITS0             1                                  
4              Slave Board BITS1             1                                  
5              Left Frame Clock              1                                  
6              Right Frame Clock             1                                  
7              FSU                           1                                  
8              Slave Board FSU               1                                  
Table 3-103  Description of the display clock wait-to-restore command output

Item

Description

Reference

Number of the clock source.

Clock Source

Name of a clock source.

WTR(unit:minute)

WTR time of a clock source.

Related Topics

snmp-agent trap enable feature-name clock

Function

Using the snmp-agent trap enable feature-name clock command, you can enable the trap function of the clock module.

Using the undo snmp-agent trap enable feature-name clock command, you can disable the trap function of the clock module.

By default, the trap function of the clock module is disabled.

Format

snmp-agent trap enable feature-name clock

undo snmp-agent trap enable feature-name clock

Parameters

None

Views

System view

Default Level

2: Configuration level

Usage Guidelines

After the snmp-agent trap enable feature-name clock command is used, the trap function of the clock module is enabled.

To view whether "snmp-agent trap enable feature-name clock" exists, you can run the display current-configuration | include snmp command in all views. If the item exists, it indicates that the trap function of the current clock module is enabled.

Example

# Enable the trap function of the clock module.

<HUAWEI> system-view
[HUAWEI] snmp-agent trap enable feature-name clock
Translation
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Updated: 2019-10-18

Document ID: EDOC1000178288

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