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Configuration Guide - Device Management

CloudEngine 12800 and 12800E V200R003C00

This document describes the configurations of Device Management, including device status query, hardware management, Information Center Configuration, NTP, Synchronous Ethernet Configuration, Fault Management Configuration, Energy-Saving Management Configuration, Performance Management Configuration, Maintenance Assistant Configuration, and OPS Configuration.

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Clock Synchronization Modes

Clock Synchronization Modes

Two clock synchronization modes are available on a communications network: pseudo synchronization and master-slave synchronization.

Pseudo Synchronization

In pseudo synchronization mode, each switching site has its own clock with very high accuracy and stability and does not synchronize their clocks with each other. There is a small difference in the clock frequency or phase among the clocks of the switching sites. This difference does not affect service transmission and can be ignored.

Pseudo synchronization is often used on communications networks between countries. Cesium clocks are usually used in the countries.

Master-Slave Synchronization

Master-Slave Synchronization Modes

In master-slave synchronization mode, a master clock of high accuracy is set on a network and traced by every site. Each sub-site traces the clock of the upper-level site. In this way, the clock is finally synchronized to end network elements.

Master-slave synchronization is often used on communications networks inside a country or region. There is one master clock of high accuracy on the communications network of a country or region, and other network elements on the network use the master clock as the reference clock.

Master-slave synchronization is classified into direct and hierarchical modes.
  • Direct master-slave synchronization

    Figure 5-3 shows direct master-slave synchronization. All slave clocks synchronize with the master clock. Direct master-slave synchronization is applicable to simple networks.
    Figure 5-3 Direct master-slave synchronization
  • Hierarchical master-slave synchronization

    Figure 5-4 shows hierarchical master-slave synchronization. The clocks are classified into three levels: level-1 master clock, level-2 slave clock, and level-3 slave clock. The level-2 slave clock synchronizes with the level-1 master clock, and the level-3 slave clock synchronizes with the level-2 slave clock. Hierarchical master-slave synchronization is applicable to large and complex networks.
    Figure 5-4 Hierarchical master-slave synchronization
Master-Slave Synchronization Reliability

To improve master-slave synchronization reliability, two master clocks are set on the network: one clock as the active master clock, and the other as the standby master clock. Both the active and standby master clocks are cesium clocks.

Under normal circumstances, all network elements trace the active master clock. If the active master clock becomes faulty, the standby master clock provides the reference clock for the entire network. After the active master clock recovers, it becomes the reference clock again.

Slave Clock Working State
In master-slave synchronization mode, a slave clock may work in any of the following states:
  • Lock

    The slave clock traces and locks the clock source provided by the clock of the upper level. The clock source may be provided either by the active master clock or by the internal clock source of the upper-level network element.

  • Hold

    If all the reference clocks are lost, the slave clock enters the hold state. In this situation, the oscillator of the clock chip on the slave clock uses the last frequency stored before the reference clocks are lost as the reference clock. In addition, the slave clock provides the clock signals that conform to the source reference clock to ensure that there is a small difference between the frequency of the provided clock signals and that of the reference clock. The accuracy of the clock in the hold state cannot keep for a long time because the inherent oscillation frequency of the oscillator may have a drift.

    In the hold state, if the slave clock locks the clock source provided by the clock of the upper level again, the slave clock changes to the lock state. Otherwise, it enters the free state.

  • Free

    After losing all external reference clocks, the slave clock loses the clock reference memory or retains the hold state for a long time. As a result, the oscillator inside the slave clock works in the free state.

Updated: 2019-05-05

Document ID: EDOC1100004193

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