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Configuration Guide - Device Management

CloudEngine 12800 and 12800E V200R003C00

This document describes the configurations of Device Management, including device status query, hardware management, Information Center Configuration, NTP, Synchronous Ethernet Configuration, Fault Management Configuration, Energy-Saving Management Configuration, Performance Management Configuration, Maintenance Assistant Configuration, and OPS Configuration.

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Clock Synchronization Implementation

Clock Synchronization Implementation

Synchronous Ethernet uses physical-layer bit streams to carry and recover frequency information, similar to traditional Synchronous Digital Hierarchy (SDH) synchronization. Figure 5-2 shows principles of synchronous Ethernet:
  • In the transmitting direction: The high-accuracy clock (master clock) traced by Device1 is injected into the PHY chip of an Ethernet interface card on Device1, and the PHY chip places high-accuracy clock information into the serial bit stream of the Ethernet line and sends the serial bit stream so that downstream nodes can obtain the information.
  • In the receiving direction: The PHY chip of an Ethernet interface card on Device2 extracts clock information from the serial bit stream of the Ethernet line and uses the automatic clock source selection algorithm to select a clock source with the highest accuracy and sends the clock source to the system phase-locked loop (PLL). In this case, you can manually or forcibly specify a clock source to be traced. The system PLL then traces the clock source and generates a high-accuracy system clock for each Ethernet interface card.
Figure 5-2 Clock synchronization principles

Updated: 2019-05-05

Document ID: EDOC1100004193

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