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OSN 500 550 580 V100R008C50 Alarms and Performance Events Reference 02

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ACR_LOCK_FAIL

ACR_LOCK_FAIL

Description

The ACR_LOCK_FAIL is an alarm indicating a failure to lock the IEEE 1588 ACR. This alarm is reported when the NE works in IEEE 1588 ACR mode and the clock fails to be locked.

Attribute

Alarm Severity Alarm Type

Major

Equipment alarm

Parameters

When you view an alarm on the network management system, select the alarm. In the Alarm Details field display the related parameters of the alarm. The alarm parameters are in the following format: Alarm Parameters (hex): parameter1 parameter2...parameterN. For details about each parameter, refer to the following table.

Name Meaning

Parameter 1

Indicates the alarm cause.

  • 0x01: The phase-locked loop (PLL) is in holdover or free-run mode.
  • 0x02: The Sync timestamp remains unchanged when the Precision Time Protocol (PTP) clock is synchronized.
  • 0x03: The phase discrimination value per unit of time exceeds the upper threshold.
  • 0x04: The IEEE 1588 ACR algorithm is in the quick lockout phrase when the clocks are synchronized by means of IEEE 1588 ACR.

Impact on the System

When this alarm occurs, services may happen to pointer justifications or bit errors.

Possible Causes

The possible causes of the ACR_LOCK_FAIL alarm are as follows:

  • Cause 1: The IEEE 1588 ACR algorithm is in the quick lockout phrase when the clocks are synchronized by means of IEEE 1588 ACR.
  • Cause 2: A fault occurs on the main control board of the NE or its upstream NE or the clock interface board.
  • Cause 3: The third-party packet delay variation (PDV) that clocks traverse is overlarge.

Procedure

  1. Cause 1: The IEEE 1588 ACR algorithm is in the quick lockout phrase when the clocks are synchronized by means of IEEE 1588 ACR.
    1. If the value of the parameter is 0x04, you do not need to handle the alarm. About 15 minutes later, check whether the alarm is cleared.
    2. If the alarm persists, go to 2.
  2. Cause 2: A fault occurs on the main control board of the NE or its upstream NE or the clock interface board.
    1. Check whether alarms related to hardware, such as HARD_BAD, are reported by the main control board of the NE or its upstream NE or the clock interface board. If yes, clear these alarms first.
    2. Check whether the alarm is cleared. If the alarm persists, go to 3.
  3. Cause 3: The third-party packet delay variation (PDV) that clocks traverse is overlarge.
    1. Check whether the PDV of the NE is overlarge by performance event CURPOSITIVEPDV. If yes, optimize the PDV of the third-party network.
    2. Then, check whether the alarm is cleared. If the alarm persists, contact Huawei technical support engineers to handle the alarm.

Related Information

None.

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Updated: 2019-01-21

Document ID: EDOC1100020975

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