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OSN 500 550 580 V100R008C50 Alarms and Performance Events Reference 02

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Huawei uses machine translation combined with human proofreading to translate this document to different languages in order to help you better understand the content of this document. Note: Even the most advanced machine translation cannot match the quality of professional translators. Huawei shall not bear any responsibility for translation accuracy and it is recommended that you refer to the English document (a link for which has been provided).
Bit Errors

Bit Errors

Bit errors are detected through the parity check of B1, B2, B3 and V5 bytes.

Generation Mechanism

The SDH system adopts bit interleaved parity (BIP) to detect bit errors. The BIP is performed on the BIP matrix of the regenerator section (RS), multiplex section (MS), higher order path, and lower order path using the B1, B2, B3, and V5 bytes respectively.

The B1 byte is used for error monitoring in the RS. This function is performed by using a bit interleaved parity 8 (BIP-8) code with even parity. The working mechanism of the B1 byte is as follows:
  1. At the transmit end, the BIP-8 is computed for all the scrambled bytes of the current frame (frame N) and the result is stored in the B1 byte of the next frame (frame N+1) to be scrambled.
  2. At the receive end, the BIP-8 is computed for all bits of the current frame (frame N-1) to be descrambled and the result is compared with the value of the B1 byte of the next descrambled frame (frame N).
  3. If the two values are different, exclusive-OR operation is conducted on them. The number of "1"s in the result is the number of errored blocks in the frame during the transmission.
The B2 byte is used to error monitor in the MS, and the working mechanism is similar to that of the B1 byte. The B1 byte monitors the errors that occur in the entire STM-N frame during the transmission. One STM-N frame has only one B1 byte. The B2 byte monitors the errors that occur in every STM-1 frame of the STM-N frame. The STM-N frame contains Nx3 B2 bytes. Every three B2 bytes correspond to one STM-1 frame. For example, there are three B2 bytes for one STM-1 frame. The working mechanism of the B2 byte is as follows:
  1. At the transmit end, the BIP-24 is computed for all bits of the previous STM-1 frame except the regenerator section overhead (RSOH), and the result is stored in the B2 bytes of the current frame to be scrambled.
  2. At the receive end, the BIP-24 is computed for all bits of the current descrambled STM-1 frame except the RSOH, and exclusive-OR operation is conducted between the parity result and the B2 bytes in the next descrambled STM-1 frame.
  3. The number of "1"s in the result of the exclusive-OR operation is the number of errored blocks that occur in this STM-1 frame within the STM-N frame during the transmission. A maximum of 24 errored blocks can be detected.

The B3 byte is used for monitoring the bit errors of the VC-4 or the 140 Mbit/s signal within the STM-N frame during transmission. The monitoring mechanism of the B3 byte is similar to that of the B1 and B2 bytes; however, it is used to perform the BIP-8 parity for the VC-4 frame.

The V5 byte performs the functions of error monitoring, signal labeling, and VC-12 path status indicating. Bits 1-2 are used to perform the BIP-2 monitoring of bit errors in the VC-12 within the STM-N frame. If the receive end detects errored blocks, the number of such blocks are displayed in the performance events at the local end. At the same time, bit 3 of the V5 byte reports the lower order path remote error indication (LP_REI) to the transmit end, and the corresponding number of errored blocks are displayed in the performance events at the transmit end.

Error Detection and Report

Figure 1-9 shows the error detection relationship and location.

Figure 1-9  Error detection relationship and location

The modules in Figure 1-9 are defined as follows:

  • RST is regenerator section termination.
  • MST is multiplex section termination.
  • HPT is higher order path termination.
  • LPT is lower order path termination.

The B1, B2, B3 and V5 bit errors are monitored between these terminations. Figure 1-9 shows that bit errors that occur in the lower order path cannot be detected in the higher order path, MS, or RS. If bit errors occur in the RS, bit errors are triggered in the MS, higher order path, and lower order path.

Generally, higher order bit errors can trigger lower order bit errors. If the B1 bit error occurs, the B2, B3 and V5 bit errors are generated. If the V5 bit error occurs, B3, B2 and B1 bit errors are not necessarily generated.

When the SDH system detects errors, it reports the error performance events or alarms, and notifies the remote end of error detection through overhead bytes.

Terms

Table 1-2 lists the relevant terms.

Table 1-2  Bit error terms
Term Description
BE Block error. It indicates that one or more bits have errors.
BBE Background block error. It indicates an errored block occurring outside the period of UAT and SES.
FEBBE Far end background block error. It indicates that a BBE event is detected at the far end.
ES Errored second. It indicates a certain second that is detected with one or more errored blocks.
FEES Far end errored second. It indicates that an ES event is detected at the far end.
SES Severely errored second. It indicates a certain second, which contains more than 30% errored blocks or at least one serious disturbance period (SDP). The SDP is a period of at least four consecutive blocks or 1 ms (taking the longer one) where the error ratios of all the consecutive blocks are more than or equal to 10-2 or a loss of signal occurs.
FESES Far end severely errored second. It indicates an SES event that is detected at the far end.
CSES Consecutive severely errored second. It indicates the SES events that occur consecutively, but last less than 10 seconds.
FECSES Far end consecutive severely errored second. It indicates a CSES event that is detected at the far end.
UAS Unavailable second. A period of 10 consecutive seconds during which the bit error ratio per second of the digital signal in either of the transmission directions of a transmission system is inferior to 10-3. These 10 seconds are considered to be part of the unavailable time.

Relationship with Alarms

Upon detecting errors, the local end of the SDH system reports an alarm or performance event, and reports the error detection information to the remote end through overhead bytes. According to the performance events or alarms reported from the local and remote ends, you can determine the faulty section of the path or the signal directions where errors occur. Table 1-3 lists the alarms and performance events related to bit errors.

Table 1-3  Alarms and performance events related to bit errors
Item Performance Event Alarm
If bit errors cross the threshold at the local end, the local end reports the relevant event. If bit errors cross the threshold at the local end, the opposite end reports the relevant event. If bit errors cross the threshold at the local end, the local end reports the relevant alarm. If bit errors exceed the threshold at the local end, the opposite end reports the relevant alarm.
Regenerator section RSBBE - B1_SD/B1_EXC -
Multiplex section MSBBE MSFEBBE B2_SD/B2_EXC MS_REI
Higher order path HPBBE HPFEBBE B3_SD/B3_EXC HP_REI
Lower order path LPBBE LPFEBBE BIP_SD/BIP_EXC LP_REI

If the B1 byte recovered from the STM-N signal is inconsistent with the BIP-8 computing result of the previous STM-N frame, the B1 bit error occurs.

If the B2 byte recovered from the STM-N signal is inconsistent with the BIP-24 computing result of the previous STM-N frame (all bits expect the RSOH), the B2 bit error occurs.

If the B3 byte recovered from the HPOH is inconsistent with BIP-8 computing result of the VC-4 signal of the previous frame, the B3 bit error occurs.

If bit 1 and bit 2 of the V5 byte that is restored from the LPOH are inconsistent from the BIP-2 computing result of the VC-12 signal in the previous frame, the BIP errors are reported.

If B1, B2 and B3 bit errors cross the 10-6 threshold, alarms such as the B1_SD, B2_SD, B3_SD occur. If B1, B2 and B3 bit errors cross the 10-3 threshold, alarms such as the B1_EXC, B2_EXC and B3_EXC occur.

When B1 detects 10 consecutive SESs in the RS, it indicates that an RSUAT event occurs.

When B2 detects 10 consecutive SESs in the MS, it indicates that an MSUAT event occurs.

When B3 detects 10 consecutive SESs, it indicates that an HPUAT event occurs.

When V5 detects 10 consecutive SESs, it indicates that an LPUAT event occurs.

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Updated: 2019-01-21

Document ID: EDOC1100020975

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