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OSN 500 550 580 V100R008C50 Alarms and Performance Events Reference 02

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Huawei uses machine translation combined with human proofreading to translate this document to different languages in order to help you better understand the content of this document. Note: Even the most advanced machine translation cannot match the quality of professional translators. Huawei shall not bear any responsibility for translation accuracy and it is recommended that you refer to the English document (a link for which has been provided).
HPBBE

HPBBE

Description

The HPBBE event indicates the higher order path background block error.

Attribute

Performance Event ID Performance Event Type

0x30

SDH performance event

Impact on the System

If bit errors occur in the services, identify the causes and rectify the fault immediately. These operations help to prevent alarms and to ensure signal transmission quality. If bit errors exceed the B3 error threshold and degrade threshold, the B3_EXC and B3_SD alarms will be generated.

Possible Causes

The HPBBE event indicates bit errors that are detected in a verification period excluding the higher order path unavailable time and higher order path severely errored second.

External causes:

  • The fiber performance deteriorates, and the fiber has high attenuation.

  • The fiber connector is dirty or incorrect.
  • The equipment is incorrectly grounded.
  • A severe interference source is present near the equipment.
  • The ambient temperature is out of the specified temperature range for the equipment.

Equipment problems:

  • The signal attenuation on the receive side of the line board is excessive, the transmit circuit at the opposite end is faulty, or the receive circuit at the local end is faulty.

  • The clock synchronization performance is poor.
  • The cross-connect unit and the line board fail to properly work together.
  • The board becomes faulty, or the board performance deteriorates.

Related Alarms

Alarm Name Correlation

B3_EXC

B3 errors threshold crossing

B3_SD

Signal degrade (B3)

Procedure

  1. Eliminate external causes, such as incorrect grounding, high ambient temperature, or low or high received optical power of the line board. Then, check whether bit errors occur on the line boards.
  2. If all the line boards of an NE have bit errors, the clock unit may be faulty. Replace the system control, cross-connect, and timing board.
  3. If only a line board reports bit errors, the local line board, the line board on the opposite NE, or fibers are faulty. Perform loopbacks to locate the faulty board, and replace the faulty board if any is found. If fibers are found faulty, replace the fibers.

Related Information

None.

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Updated: 2019-01-21

Document ID: EDOC1100020975

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