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OSN 500 550 580 V100R008C50 Alarms and Performance Events Reference 02

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Huawei uses machine translation combined with human proofreading to translate this document to different languages in order to help you better understand the content of this document. Note: Even the most advanced machine translation cannot match the quality of professional translators. Huawei shall not bear any responsibility for translation accuracy and it is recommended that you refer to the English document (a link for which has been provided).
LPSES

LPSES

Performance Event Meaning

The LPSES event indicates the lower-order path severely errored second.

Performance Event Attributes

Performance Event ID Performance Event Type

0x92

SDH performance event

Impact on the System

If bit errors occur in the services, identify the causes and rectify the fault immediately. Otherwise, alarms will be generated and the signal transmission quality will be affected. If bit errors exceed the BIP bit threshold and degrade threshold, the BIP_EXC and BIP_SD alarms will be generated.

Possible Causes

The LPSES event occurs when one of the following requirements is met: 1. Not less than 30% bit errors are detected in one second. 2. At least one severely disturbed period (SDP) occurs. SDP occurs when the BER of all the continuous blocks in a period of at least four consecutive blocks or 1 ms (select the longer period) is lower than 10-2, or when the LP_UNEQ, LP_TIM, TU_AIS or TU_LOP alarm occurs on the path. When the service is at the VC-12 level, the first two bits of the V5 byte are verified. When the service is at the VC-3 level, the B3 byte is verified.

External causes:

  • The fiber performance is degraded, and the fiber has high attenuation.

  • The fiber connector is dirty or incorrect.
  • The equipment is poorly grounded.
  • A severe interference source is present near the equipment.
  • The working temperature is high or low, and the opposite equipment cannot tolerate such temperature.

Equipment problems:

  • The signal attenuation on the receive side of the line board is excessive, the transmit circuit at the opposite end is faulty, or the receive circuit at the local end is faulty.

  • The synchronization performance of the clock is poor.
  • The cross-connect unit and the line unit or the cross-connect unit and the tributary unit poorly match.
  • The tributary board is faulty.
  • The board becomes faulty, or the performance of the board is degraded.

Relevant Alarms

Alarm Name Correlation

BIP_EXC

Indicates that the BIP bit errors cross the threshold when the service level is VC-12.

BIP_SD

Indicates that the BIP signal degraded when the service level is VC-12.

B3_EXC

Indicates BIP excessive errors when the service level is VC-3.

B3_SD

Indicates that the higher-order path (B3) signal degraded when the service level is VC-3.

LP_UNEQ

Indicates that the lower-order path is not equipped.

LP_TIM

Indicates that the lower-order path tracking identifiers mismatch.

TU_AIS

Indicates the TU alarm indication signal.

TU_LOP

Indicates the TU loss of pointer.

Procedure

  1. See LPES.

Reference

None.

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Updated: 2019-01-21

Document ID: EDOC1100020975

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