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OSN 500 550 580 V100R008C50 Alarms and Performance Events Reference 02

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Huawei uses machine translation combined with human proofreading to translate this document to different languages in order to help you better understand the content of this document. Note: Even the most advanced machine translation cannot match the quality of professional translators. Huawei shall not bear any responsibility for translation accuracy and it is recommended that you refer to the English document (a link for which has been provided).
Downlink Signal Flow

Downlink Signal Flow

By processing lower order overhead bytes, the system detects alarms and performance events in the lower order downlink signal flow.

HPA and LPT

The HPA and LPT modules are key lower order functional modules, which process most lower order overhead bytes.

The lower order overhead bytes include the following:
  • Lower order path pointer indication bytes (V1, V2, and V3)
  • Path state and signal label byte (V5)
  • Lower order path identifier (J2)

The VC-4 signal from the cross-connect unit is transmitted to the HPA.

The HPA demaps the VC-4s into VC-12s. The pointers of all VC-12s are decoded to provide the per-byte frame offset information between the VC-4s and the VC-12s.

When the NE clock at the TU-12 assembler differs from the local reference clock, continuous pointer justification is performed. The positive TU pointer justification (TUPJCHIGH) and the negative TU pointer justification (TUPJCLOW) are detected in the downlink signal flow.

If an incorrect H4 multiframe byte sequence is detected in the downlink direction, the HP_LOM alarm is reported.

If the lower order pointer byte V1 or V2 is all "1"s, a TU_AIS alarm is reported. If the value of V1 or V2 is illegal, a TU_LOP alarm is reported. If either of these two alarms is reported, all "1"s signal is inserted into the next functional module.

In addition, if a TU_AIS alarm is generated, an AIS signal is inserted in the downlink data. At the same time, an LP_RDI alarm is reported; that is, bit 8 of the V5 byte is set to "1".

The VC-12 signal is transmitted to the LPT module for V5 byte processing.

Figure 1-5 shows the structure of the V5 byte.

Figure 1-5  Structure of the V5 byte

If bits 5-7 of the V5 byte in the downlink signal flow are detected to be "000", the lower order paths are not equipped (LP_UNEQ). If a signal label mismatch occurs, an LP_SLM alarm is reported.

The path RDI information in bit 8 of the V5 byte is terminated, and an LP_RDI is reported.

Error monitoring bits 1 and 2 of the V5 byte are detected and the BIP-2 for the VC-12 signal is calculated. The BIP-2 value that is calculated for the current frame is compared with bits 1 and 2 of the V5 byte recovered from the next frame. An LPBBE is reported if they are not the same. Meanwhile, bit 3 of the V5 byte is restored. If it is "1", BIP-2 errors occur at the remote end and an LPFEBBE is reported at the remote end.

NOTE:

Bit 4 of the V5 byte is not used.

If 10 consecutive SESs occur during the BIP-2 monitoring process, an LVCUATEVENT is reported.

At the same time, the lower order path identifier (J2) is recovered and the value of the received J2 byte is checked. If the received J2 byte is different from the expected value, an LP_TIM alarm is reported.

LPA and PPI

The C-12 data that is processed in the previous procedure is transmitted to the LPA.

The subscriber data stream and the related clock reference signals are restored from the container at the same time, and are transmitted to the PDH physical interface (PPI) as data and timing reference.

After being processed by the LPA, the data and the clock signal are transmitted to the PPI and form a 2048 kbit/s signal.

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Updated: 2019-01-21

Document ID: EDOC1100020975

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