PCIe Slots
The following tables describe the mapping between the PCIe slots and the CPUs and mezzanine cards, and list the PCIe standards.
PCIe Device |
CPU |
PCIe Standard |
Connector Width |
Bus Width |
Port Number |
Device Size |
|---|---|---|---|---|---|---|
RAID controller card |
CPU 1 |
PCIe 3.0 |
x8 |
x8 |
Port 1A |
Non-standard device |
Mezzanine card 1 |
CPU 1 |
PCIe 3.0 |
2 x16 |
2 x16 |
Port 2A, Port 3A |
Non-standard device |
Mezzanine card 2 |
CPU 2 |
PCIe 3.0 |
2 x16 |
2 x16 |
Port 2A, Port 3A |
Non-standard device |
NVMe SSD 4 |
CPU 1 |
PCIe 3.0 |
x4 |
x4 |
Port 1C |
2.5-inch drive |
NVMe SSD 5 |
CPU 1 |
PCIe 3.0 |
x4 |
x4 |
Port 1D |
2.5-inch drive |
NVMe SSD 6 |
CPU 2 |
PCIe 3.0 |
x4 |
x4 |
Port 1A |
2.5-inch drive |
NVMe SSD 7 |
CPU 2 |
PCIe 3.0 |
x4 |
x4 |
Port 1B |
2.5-inch drive |
NVMe SSD 8 |
CPU 2 |
PCIe 3.0 |
x4 |
x4 |
Port 1C |
2.5-inch drive |
NVMe SSD 9 |
CPU 2 |
PCIe 3.0 |
x4 |
x4 |
Port 1D |
2.5-inch drive |
NOTE: NVMe SSDs 4 to 5 are connected to CPU 1, and NVMe SSDs 6 to 9 are connected to CPU 2. You are advised to configure NVMe SSDs based on the bandwidth balance.
PCIe Device |
CPU |
PCIe Standard |
Connector Width |
Bus Width |
Port Number |
Device Size |
|---|---|---|---|---|---|---|
PCIe slot 1 |
CPU 1 |
PCIe 3.0 |
x16 |
x16 |
Port 3A |
Full-height full-length dual-slot card |
PCIe slot 2 |
CPU 1 |
PCIe 3.0 |
x16 |
x16 |
Port 3A |
Full-height full-length dual-slot card |
PCIe slot 3 |
CPU 1 |
PCIe 3.0 |
x16 |
x16 |
Port 3A |
Full-height full-length dual-slot card |
PCIe slot 4 |
CPU 1 |
PCIe 3.0 |
x16 |
x16 |
Port 3A |
Full-height full-length dual-slot card |
PCIe slot 5 |
CPU 1/CPU 2a |
PCIe 3.0 |
x16 |
x16 |
Port 3A |
Full-height full-length dual-slot card |
PCIe slot 6 |
CPU 1/CPU 2a |
PCIe 3.0 |
x16 |
x16 |
Port 3A |
Full-height full-length dual-slot card |
PCIe slot 7 |
CPU 1/CPU 2a |
PCIe 3.0 |
x16 |
x16 |
Port 3A |
Full-height full-length dual-slot card |
PCIe slot 8 |
CPU 1/CPU 2a |
PCIe 3.0 |
x16 |
x16 |
Port 3A |
Full-height full-length dual-slot card |
PCIe slot 9 |
CPU 1 |
PCIe 3.0 |
x16 |
x16 |
Port 3A |
Full-height full-length single-slot card |
I/O slot 1 |
CPU 1 |
PCIe 3.0 |
x16 |
x16 |
Port 3A |
Half-height half-length single-slot card |
I/O slot 2 |
CPU 1 |
PCIe 3.0 |
x16 |
x16 |
Port 3A |
Half-height half-length single-slot card |
I/O slot 3 |
CPU 2 |
PCIe 3.0 |
x16 |
x16 |
Port 3A |
Half-height half-length single-slot card |
I/O slot 4 |
CPU 1/CPU 2a |
PCIe 3.0 |
x16 |
x16 |
Port 3A |
Half-height half-length single-slot card |
A: In logical topology 1, this slot is managed by CPU 1; in logical topology 2, this slot is managed by CPU 2. |
||||||
NOTE: - The mezzanine cards to which PCIe slots 5 to 8 and I/O slot 4 are connected vary depending on the logical topology. For details, see Logical Structure.
- PCIe slot 9 and I/O slot 1 are mutually exclusive and cannot be used at the same time. By default, I/O slot 1 is selected.
- I/O slot 2 is available only in logical topology 2.
- PCIe cards in PCIe slots 1 to 9 require Huawei-customized brackets.
PCIe Device |
CPU |
PCIe Standard |
Connector Width |
Bus Width |
Port Number |
Device Size |
|---|---|---|---|---|---|---|
GPU 1 |
CPU 1 |
PCIe 3.0 |
x16 |
x16 |
Port 2A |
SXM2 |
GPU 2 |
CPU 1 |
PCIe 3.0 |
x16 |
x16 |
Port 3A |
SXM2 |
GPU 3 |
CPU 1 |
PCIe 3.0 |
x16 |
x16 |
Port 2A |
SXM2 |
GPU 4 |
CPU 1 |
PCIe 3.0 |
x16 |
x16 |
Port 3A |
SXM2 |
GPU 5 |
CPU 2 |
PCIe 3.0 |
x16 |
x16 |
Port 2A |
SXM2 |
GPU 6 |
CPU 2 |
PCIe 3.0 |
x16 |
x16 |
Port 3A |
SXM2 |
GPU 7 |
CPU 2 |
PCIe 3.0 |
x16 |
x16 |
Port 2A |
SXM2 |
GPU 8 |
CPU 2 |
PCIe 3.0 |
x16 |
x16 |
Port 3A |
SXM2 |
I/O 1 |
CPU 1 |
PCIe 3.0 |
x16 |
X16 |
Port 2A |
Half-height half-length single-slot card |
I/O 2 |
CPU 1 |
PCIe 3.0 |
x16 |
x16 |
Port 3A |
Half-height half-length single-slot card |
I/O 3 |
CPU 2 |
PCIe 3.0 |
x16 |
x16 |
Port 2A |
Half-height half-length single-slot card |
I/O 4 |
CPU 2 |
PCIe 3.0 |
x16 |
x16 |
Port 3A |
Half-height half-length single-slot card |
PCIe slot |
CPU 1 |
PCIe 3.0 |
X8 |
X8 |
Port 2A |
Full-height full-length single-slot card |
Previous
