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NE40E V800R010C10SPC500 Feature Description - Virtual-Cluster-Chassis 01

This is NE40E V800R010C10SPC500 Feature Description - Virtual-Cluster-Chassis
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Concepts Related to Virtual Cluster

Concepts Related to Virtual Cluster

This section describes the basic concepts of the virtual cluster technology, including physical topology and the chassis interconnection mode.

Physical Topology

A virtual cluster only supports clusters consisting of two chassis. The topology is shown in the following figure.

Two devices form a cluster by connecting control and data channels in back-to-back mode.

In a two-chassis cluster:
  • One of the two chassis acts as the master chassis, and the other as a backup.
  • Each chassis has two MPUs. One is the master MPU and the other is the slave MPU.
  • The master MPU of the master chassis acts as the master MPU for the cluster system as a whole, and the master MPU of the backup chassis works in hot backup mode for the cluster system. Each chassis and slave MPU acts as the cold backup MPU of the cluster system.
  • The interface boards on the main and standby chassis act as the interface board for the cluster system as a whole.

The current version supports the following chassis: NE40E-X8, NE40E-X16, NE40E-X8A, and NE40E-X16A.

Chassis Interconnection Modes

In a two-chassis cluster, the chassis interconnection is logically divided into two planes:

  • Connected control plane (control channel): used for communication between processors within the virtual cluster, including the independent control channel connection (with dedicated connections) and multiplexing control channel connection (using inband mode, and control plane information is transmitted through a data channel). Currently, only the independent control channel connection is supported.
  • Connected data plane (data channel): used for inter-chassis data forwarding in the virtual cluster. It requires a dedicated connection.

Independent control channel connection

Connection mode:

Each chassis has two MPUs, and each MPU has two cascading interfaces used for the control plane. The MPU cascading interfaces are optical interfaces, and use pluggable optical modules which can be directly connected using optical fibers.

The connection requirements for channel protection are as follows:

  • Two interfaces on each MPU of one chassis must be connected with each of the two MPUs of the other chassis. As shown in the following figure, four cables are cross-connected. This connection mode ensures that the virtual cluster can work properly if a board or link is faulty.

NOTE:
You are advised to connect MPUs/IPUs based on channel protection requirements to ensure virtual cluster reliability.

Data channel connection

Connection mode:

Virtual cluster does not require dedicated interconnection boards. A common interface board can be used as the interconnection board. Interface boards do not need to be used solely for interconnection. Some interfaces can be used to interconnect while other interfaces are used to run services. Interconnection interfaces on interface boards of two devices are directly connected through optical modules and optical fibers.

The connection requirements for channel protection are as follows:

  • Per-flow load balancing is performed between data links of the two chassis.
  • The bandwidth of each data link must be the same. Otherwise, load balancing is uneven.
  • Data links can be dynamically added or deleted without affecting services.
  • Data links must be deployed between boards to ensure reliability.

The following flowcharts show chassis interconnection. You can adjust the connections based on site requirements.

Figure 2-1 Flowchart for chassis interconnection of a virtual cluster system
  • The red line indicates the control channel connection, and the green line indicates the data channel connection.
  • The connection principles are as follows: Four cables are cross-connected for control channel connections, and cross-board connections are used for data channels to ensure virtual cluster reliability.
  • For details about MPU interfaces, see Hardware Description > Boards > Control Plane.
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Updated: 2019-01-03

Document ID: EDOC1100055054

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