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NE20E-S2 V800R010C10SPC500 Configuration Guide - System Management 01

This is NE20E-S2 V800R010C10SPC500 Configuration Guide - System Management
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Configuring the Manual or Forcible Clock Source Selection Mode

Configuring the Manual or Forcible Clock Source Selection Mode

Usage Scenario

By default, the NE20E uses the automatic clock source selection algorithm to determine a clock source to be traced for system or 2M phase-locked loop (PLL) clocks. You can also manually or forcibly specify a clock source to be traced based on the quality level of clock sources.

Pre-configuration Tasks

None

Configuration Procedures

Perform the following configuration tasks (except checking the configuration) based on the applicable environment:

Configuring a Clock Source

Context

Before configuring clock synchronization on the NE20E, configure a clock source. The NE20E supports building integrated timing supply (BITS), Precision Time Protocol (PTP), and line clock sources. Perform one of the following configurations based on the clock source used on a clock synchronization network:

Procedure

  • Configure a BITS clock source.
    1. Run system-view

      The system view is displayed.

    2. Run clock bits-type bits0 { 2mhz | 2mbps }

      A signal type is configured for the BITS clock source.

    3. (Optional) Run clock sa-bit { sa4 | sa5 | sa6 | sa7 | sa8 } source bits0

      A timeslot is configured for the BITS clock source to extract SSM levels.

    4. (Optional) Run clock source bits0 ssm { dnu | prc | sec | ssua | ssub | unk }

      An SSM level is configured for the BITS clock source.

      If the signal type of the BITS clock source is 2mhz, the BITS clock source cannot extract SSM levels from clock signals. If you have configured SSM levels to participate in clock source selection, run this command to manually configure an SSM level for the BITS clock source.

    5. (Optional) Run clock bits output-threshold { prc | ssua | ssub | sec | dnu }

      A threshold is configured for the SSM level of clock signals sent by the BITS clock source.

      If the SSM level of clock signals sent by the BITS clock source is lower than the configured threshold, the BITS clock source stops sending clock signals.

    6. Run commit

      The configuration is committed.

  • Configure a PTP clock source.
    1. Run system-view

      The system view is displayed.

    2. Run ptp device-type

      Set a clock mode for a 1588v2 device.

    3. Run ptp enable

      PTP is enabled.

    4. Run interface interface-type interface-number

      Log in an interface.

    5. Run ptp enable

      Enable 1588v2 on a specific interface.

    6. Run quit

      Back to the system view.

    7. Run clock source ptp synchronization enable

      Clock synchronization is enabled for the PTP clock source.

    8. Run clock source ptp priority source ptp priority priority-value

      A priority is configured for the PTP clock source.

      A smaller value indicates a higher priority.

    9. (Optional) Run clock source ptp ssm { dnu | prc | sec | ssua | ssub | unk }

      An SSM level is configured for the PTP clock source.

      If you have configured SSM levels to participate in clock source selection, run this command to manually configure an SSM level for the PTP clock source.

    10. (Optional) Run clock source ptp clock-id clock-id

      A clock ID is configured for the PTP clock source.

      If you have enabled the extended SSM function, configure a clock ID for the PTP clock source.

    11. Run commit

      The configuration is committed.

  • Configure a line clock source.
    1. Run system-view

      The system view is displayed.

    2. Run interface interface-type interface-number

      The interface view is displayed.

    3. Run clock synchronization enable

      Clock synchronization is enabled for the line clock source.

    4. Run clock [ 2msync-1 | 2msync-2 ] priority priority-value

      A priority is configured for the line clock source.

      A smaller value indicates a higher priority.

    5. (Optional) Run clock ssm { dnu | prc | sec | ssua | ssub | unk }

      An SSM level is configured for the line clock source.

    6. (Optional) Run clock clock-id clock-id

      A clock ID is configured for a line clock source

    7. (Optional) If two or more clock links exist between two devices, to prevent a clock loop, Run clock bundle bundle-value

      A bundle group ID is configured for the line clock source, and the line clock source is added to a bundle group.

    8. Run commit

      The configuration is committed.

Configuring the Manual or Forcible Clock Source Selection Mode

Context

By default, the NE20E uses the automatic clock source selection algorithm to determine a clock source to be traced. You can also manually or forcibly specify a clock source to be traced based on the quality level of clock sources.

If the status of a forcibly specified clock source is not normal or its SSM level is dnu, the system clock works in the hold state.

If the status of a manually specified clock source is neither normal nor holdoff, or its SSM level is not the highest, this manually specified clock source does not take effect.

Procedure

  1. Run system-view

    The system view is displayed.

  2. Run clock { manual | force } { 2msync-1 | 2msync-2 } source interface interface-type interface-numberclock { manual | force } 2msync-1 source interface interface-type interface-number

    A clock source is manually or forcibly specified for 2M synchronous PLL-1 clocks.

    NOTE:
    The clock manual source command configuration is not saved in the configuration file. You can run the display clock config command to check the configurations. If the specified clock source becomes invalid, the system automatically uses the automatic clock source selection mode. After the device is restarted, the clock manual source command configuration is not restored, and the system uses the default automatic clock source selection mode. After the device is upgraded to this version from an earlier version, the clock manual source command run in the earlier version no longer takes effect, and the system uses the default automatic clock source selection mode.

  3. Run clock { manual | force } source {bits0 | ptp | interface interface-type interface-number }

    A clock source is manually or forcibly specified for system clocks.

    NOTE:
    The clock manual source command configuration is not saved in the configuration file. You can run the display clock config command to check the configurations. If the specified clock source becomes invalid, the system automatically uses the automatic clock source selection mode. After the device is restarted, the clock manual source command configuration is not restored, and the system uses the default automatic clock source selection mode. After the device is upgraded to this version from an earlier version, the clock manual source command run in the earlier version no longer takes effect, and the system uses the default automatic clock source selection mode.

  4. Run commit

    The configuration is committed.

Verifying the Configuration of the Manual or Forcible Clock Source Selection Mode

Prerequisites

After configuring the manual or forcible clock source selection mode, verify the configuration.

Procedure

  1. Run the display clock config command to check clock source selection configurations.
  2. Run the display clock source command to check information about all clock sources, including the traced clock source.

Example

Run the display clock config command to view clock source selection configurations on the NE20E.

<HUAWEI> display clock config 
 clock freq deviation detect:disable
 clock unk map              :dnu
 system pll run mode        :normal
 bits output threshold      :dnu
source input threshold     :sec
 tod protocol               :ubx

 switch config
    sys pll                 :auto mode
    2msync-1 pll            :auto mode
    SSM control             :on
    Extend SSM control      :off
    internal clockid        :0
    switch mode             :revertive
    wtr                     :5min
    holdoff time            :1000ms

 source config
 bits0
    Sync enable
    Sa-bit                  :sa4
    Signal-type             :2mbps                           

Run the display clock source command to view information about all clock sources, including the traced clock source.

<HUAWEI> display clock source
System trace source State:    lock mode
                              into pull-in range
 Current system trace source: bits0
 Current 2M-1 trace source:   system PLL
 Frequency lock success:      yes

 Master board
 Source        Pri(sys/2m-1)   In-SSM     Out-SSM    State      Ref
 --------------------------------------------------------------------------
 bits0/          1/---         sec        dnu       normal     yes
 GE0/1/0         2/---         sec        sec       normal     yes
 GE0/2/0         3/---         sec        sec       normal     yes
 
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Updated: 2019-01-02

Document ID: EDOC1100055400

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