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NE20E-S2 V800R010C10SPC500 Configuration Guide - System Management 01

This is NE20E-S2 V800R010C10SPC500 Configuration Guide - System Management
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Configuring the Automatic Clock Source Selection Mode

Configuring the Automatic Clock Source Selection Mode

Usage Scenario

If the status or quality of clock sources on a clock synchronization network does not remain stable, configure the automatic clock source selection mode to ensure that the NE20E selects an optimal clock source.

The NE20E supports three clock source selection modes: automatic clock source selection, manual clock source selection, and forcible clock source selection. In automatic clock source selection mode, the NE20E uses the automatic clock source selection algorithm to determine a clock source to be traced. The reference factors for automatic clock source selection include priorities, synchronous status message (SSM) levels, and clock IDs of clock sources. The automatic clock source selection algorithm uses one or more of the reference factors, depending on the actual configurations.

Pre-configuration Tasks

None

Configuration Procedures

Figure 7-2 Flowchart for configuring the automatic clock source selection mode

Configuring a Clock Source

Context

Before configuring clock synchronization on the NE20E, configure a clock source. The NE20E supports building integrated timing supply (BITS), Precision Time Protocol (PTP), and line clock sources. Perform one of the following configurations based on the clock source used on a clock synchronization network:

Procedure

  • Configure a BITS clock source.
    1. Run system-view

      The system view is displayed.

    2. Run clock bits-type bits0 { 2mhz | 2mbps }

      A signal type is configured for the BITS clock source.

    3. Run clock source bits0 synchronization enable

      Enables clock synchronization for a BITS clock source.

    4. Run clock source bits0 priority priority-value

      A priority is configured for the BITS clock source.

      A smaller value indicates a higher priority.

    5. (Optional) Run clock sa-bit { sa4 | sa5 | sa6 | sa7 | sa8 } source bits0

      A timeslot is configured for the BITS clock source to extract SSM levels.

    6. (Optional) Run clock source bits0 ssm { dnu | prc | sec | ssua | ssub | unk }

      An SSM level is configured for the BITS clock source.

      If the signal type of the BITS clock source is 2mhz, the BITS clock source cannot extract SSM levels from clock signals. If you have configured SSM levels to participate in clock source selection, run this command to manually configure an SSM level for the BITS clock source.

    7. (Optional) Run clock source bits0 clock-id clock-id

      A clock ID is configured for the BITS clock source.

      If you have enabled the extended SSM function, configure a clock ID for the BITS clock source.

    8. (Optional) Run clock bits output-threshold { prc | ssua | ssub | sec | dnu }

      A threshold is configured for the SSM level of clock signals sent by the BITS clock source.

      If the SSM level of clock signals sent by the BITS clock source is lower than the configured threshold, the BITS clock source stops sending clock signals.

    9. Run commit

      The configuration is committed.

  • Configure a PTP clock source.
    1. Run system-view

      The system view is displayed.

    2. Run ptp device-type

      Set a clock mode for a 1588v2 device.

    3. Run ptp enable

      PTP is enabled.

    4. Run interface interface-type interface-number

      Log in an interface.

    5. Run ptp enable

      Enable 1588v2 on a specific interface.

    6. Run quit

      Back to the system view.

    7. Run clock source ptp synchronization enable

      Clock synchronization is enabled for the PTP clock source.

    8. Run clock source ptp priority priority-value

      A priority is configured for the PTP clock source.

      A smaller value indicates a higher priority.

    9. (Optional) Run clock source ptp ssm { dnu | prc | sec | ssua | ssub | unk }

      An SSM level is configured for the PTP clock source.

      If you have configured SSM levels to participate in clock source selection, run this command to manually configure an SSM level for the PTP clock source.

    10. (Optional) Run clock source ptp clock-id clock-id

      A clock ID is configured for the PTP clock source.

      If you have enabled the extended SSM function, configure a clock ID for the PTP clock source.

    11. Run commit

      The configuration is committed.

  • Configure a line clock source.
    1. Run system-view

      The system view is displayed.

    2. Run interface interface-type interface-number

      The interface view is displayed.

    3. Run clock synchronization enable

      Clock synchronization is enabled for the line clock source.

    4. (Optional) Run clock [ 2msync-1 ] priority priority-value

      A priority is configured for the line clock source.

      A smaller value indicates a higher priority.

    5. (Optional) Run clock ssm { dnu | prc | sec | ssua | ssub | unk }

      An SSM level is configured for the line clock source.

    6. (Optional) Run clock clock-id clock-id

      A clock ID is configured for the line clock source.

    7. (Optional) If two or more clock links exist between two devices, to prevent a clock loop, Run clock bundle bundle-value

      A bundle group ID is configured for the line clock source, and the line clock source is added to a bundle group.

    8. Run commit

      The configuration is committed.

(Optional) Configuring Parameters for Automatic Clock Source Selection

Context

When the NE20E works in automatic clock source selection mode, the configurable parameters include:
  • Frequency deviation detection
  • SSM level mapped to the clock source with an SSM level of unk
  • Maximum output SSM level of clock signals
  • Reversion mode of the clock source selection algorithm
  • Holdoff time after clock source signals are lost
  • Wait to restore (WTR) time for a status change after the clock source is restored
You can configure the function or parameters to improve the synchronization quality of a clock synchronization network and keep stable clock signals.

Procedure

  1. Run system-view

    The system view is displayed.

  2. Run clock freq-deviation-detect enable

    Frequency deviation detection is enabled.

    When frequency deviation detection is enabled, frequency deviation detection results serve as reference factors for automatic clock source selection and may affect the final clock source selection.

  3. Run clock board-freq-switch enable

    Frequency deviation-triggered clock source switching is enabled.

    After this function is enabled, if the system detects that the frequency deviation of the clock source is abnormal, it notifies the interface board where the clock source resides, triggering the interface board to select the optimal clock source for use.

  4. Run clock freq-deviation recover

    Frequency deviation status recovery is enabled for clock sources.

    A clock source can participate in reference clock source selection only when its frequency deviation status is normal.

    NOTE:
    In scenarios where frequency deviation detection and frequency deviation-triggered clock source switching are both enabled, if the frequency deviation of a clock source is detected to be abnormal, then the clock source frequency deviation status is set to be abnormal. When selecting the reference clock source, the interface board excludes this clock source from the candidate clock source list. After determining that the frequency deviation of the clock source has recovered, you can run this command to recover its frequency deviation status, so that the clock source can participate in reference clock source selection again.

  5. Run clock map unk { dnu | prc | sec | ssua | ssub }

    An SSM level is mapped to the clock source with an SSM level of unk.

    unk indicates that the clock source has an unknown SSM level. The clock source with an SSM level of unk cannot participate in clock source selection. To enable this type of clock source to participate in clock source selection, map a valid SSM level to it.

  6. Run clock max-out-ssm { prc | sec | ssua | ssub }

    The maximum output SSM level is configured for clock signals.

    By default, the SSM level that the NE20E transfers to a downstream device is the actual SSM level of clock signals. To reduce the probability that a downstream device traces clock signals with poor quality, configure a lower maximum output SSM level to limit the SSM level that the NE20E transfers to this downstream device.

  7. Run clock switch { revertive | non-revertive }

    A reversion mode is configured for the clock source selection algorithm.

    The NE20E supports the following reversion modes:

    • Revertive mode: If the optimal clock source is faulty, the NE20E uses the clock source selection algorithm to select the second optimal clock source. If the optimal clock source is restored, the NE20E automatically retraces it.
    • Non-revertive mode: If the optimal clock source is faulty, the NE20E uses the clock source selection algorithm to select the second optimal clock source. If the optimal clock source is restored, the NE20E continues to trace the second optimal clock source. If there is no the second optimal clock source to select, the NE20E select the optimal clock source.

  8. Run clock source-lost holdoff-time value

    A holdoff time after clock source signals are lost is configured.

    When clock source signals are lost, the NE20E reports status changes only after a holdoff time to instruct the clock source selection algorithm to reselect a clock source. This processing mechanism prevents the clock source selection algorithm from frequently reselecting a clock source when clock source signals are lost for a short time.

  9. Run clock wtr wtr-time

    A WTR time is configured for a status change after the clock source is restored.

    You can configure an appropriate WTR time to minimize the impact of frequent clock source status changes on clock source selection.

  10. Run commit

    The configuration is committed.

Configuring the Automatic Clock Source Selection Mode and Reference Factors

Context

The NE20E supports three clock source selection modes: automatic clock source selection, manual clock source selection, and forcible clock source selection. By default, the NE20E works in automatic clock source selection mode.

In automatic clock source selection mode, three reference factors may affect the final clock source selection. The three reference factors are priorities, synchronous status message (SSM) levels, and clock IDs of clock sources.
  • By default, the automatic clock source selection algorithm selects a clock source based on priorities of clock sources.

  • If you have configured SSM levels to participate in clock source selection, the automatic clock source selection algorithm selects a clock source based on priorities and SSM levels of clock sources.

  • If the extended SSM function is enabled, clock IDs of clock sources also participate in clock source selection. The participation of clock IDs prevents clock loops.

Procedure

  1. Run system-view

    The system view is displayed.

  2. (Optional) Run clock clear

    The clock source selection mode is restored to automatic clock source selection.

    You can run this command to restore the clock source selection mode from manual or forcible clock source selection to automatic clock source selection.

  3. Run clock ssm-control { on | off }

    SSM levels are configured to participate in automatic clock source selection.

  4. (Optional) Run clock extend-ssm-control { on | off }

    The extended SSM function is enabled so that clock IDs participate in automatic clock source selection.

  5. Run commit

    The configuration is committed.

Verifying the Configuration of the Automatic Clock Source Selection Mode

Prerequisites

After configuring the automatic clock source selection mode, verify the configuration.

Procedure

  1. Run the display clock config command to check clock source selection configurations.
  2. Run the display clock source command to check information about all clock sources, including the traced clock source.

Example

Run the display clock config command to view clock source selection configurations on the NE20E.

<HUAWEI> display clock config 
 clock freq deviation detect:disable
 clock unk map              :dnu
 system pll run mode        :normal
 bits output threshold      :dnu
source input threshold     :sec
 tod protocol               :ubx

 switch config
    sys pll                 :auto mode
    2msync-1 pll            :auto mode
    SSM control             :on
    Extend SSM control      :off
    internal clockid        :0
    switch mode             :revertive
    wtr                     :5min
    holdoff time            :1000ms

 source config
 bits0
    Sync enable
    Sa-bit                  :sa4
    Signal-type             :2mbps                           

Run the display clock source command to view information about all clock sources, including the traced clock source.

<HUAWEI> display clock source
System trace source State:    lock mode
                              into pull-in range
 Current system trace source: bits0
 Current 2M-1 trace source:   system PLL
 Frequency lock success:      yes

 Master board
 Source        Pri(sys/2m-1)   In-SSM     Out-SSM    State      Ref
 --------------------------------------------------------------------------
 bits0/          1/---         sec        dnu       normal     yes
 GE0/1/0         2/---         sec        sec       normal     yes
 GE0/2/0         3/---         sec        sec       normal     yes
 
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Updated: 2019-01-02

Document ID: EDOC1100055400

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