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NE40E-M2 V800R010C10SPC500 Configuration Guide - System Management 01

This is NE40E-M2 V800R010C10SPC500 Configuration Guide - System Management
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Huawei uses machine translation combined with human proofreading to translate this document to different languages in order to help you better understand the content of this document. Note: Even the most advanced machine translation cannot match the quality of professional translators. Huawei shall not bear any responsibility for translation accuracy and it is recommended that you refer to the English document (a link for which has been provided).
Example for Configuring Clock Synchronization on a Ring Network

Example for Configuring Clock Synchronization on a Ring Network

Networking Requirements

Figure 7-3 shows a ring network. On this network, Device A and Device C connect to one external building integrated timing supply system (BITS) each. Configure devices to trace clock signals from the BITS connected to Device A, and configure devices to trace clock signals from the BITS connected to Device C after the BITS connected to Device A fails.

Enable the devices to select clock sources based on SSM levels, helping select the best quality clock signals. This can improve the clock synchronization network.

Figure 7-3 Networking diagram of configuring clock synchronization on a ring network
NOTE:

The configurations in this example are performed on Device A, Device B, Device C, and Device D. HUAWEI NE40E-M2 Series can function as Device A, Device B, Device C, and Device D.

Interfaces 1 and 2 in this example are GE 0/1/0, GE 0/2/0, respectively.



Precautions

None

Configuration Roadmap

The configuration roadmap is as follows:

  1. Configure a clock synchronization mode and enable the devices to select clock sources based on SSM levels.
  2. Configure clock sources.
  3. Disable Device A from tracing clock signals from its connected BITS and check whether devices go to trace clock signals from the BITS connected to Device C.

Data Preparation

To complete the configuration, plan each Router's clock source priority and SSM level, as listed in Table 7-1.

Table 7-1 Clock source priority and SSM level of each Router

Router

Clock Source in Use

Priority

SSM Level

DeviceA

BITS0

1

ssua

GE 0/1/0

2

-

GE 0/2/0

-

-

DeviceB

GE 0/1/0

1

-

GE 0/2/0

2

-

DeviceC

BITS0

1

sec

GE 0/1/0

-

-

GE 0/2/0

3

-

DeviceD

GE0/1/0

1

-

GE0/2/0

2

-

Procedure

  1. Enable the devices to select clock sources based on SSM levels.

    # Configure Device A.

    <HUAWEI> system-view
    [HUAWEI] sysname DeviceA
    [HUAWEI] commit
    [~DeviceA] clock ssm-control on
    [*DeviceA] commit

    # Configure other devices by using the same method for configuring Device A.

  2. Configure clock sources.

    # Configure Device A.

    [*DeviceA] clock bits-type bits0 2mhz
    [*DeviceA] clock source bits0 priority 1
    [*DeviceA] clock source bits0 ssm ssua
    [*DeviceA] commit
    [~DeviceA] quit
    [~DeviceA] interface gigabitethernet 0/1/0
    [*DeviceA-GigabitEthernet0/1/0] clock synchronization enable
    [*DeviceA-GigabitEthernet0/1/0] clock priority 2
    [*DeviceA-GigabitEthernet0/1/0] commit
    [~DeviceA-GigabitEthernet0/1/0] quit
    [~DeviceA] interface gigabitethernet 0/2/0
    [*DeviceA-GigabitEthernet0/2/0] clock synchronization enable
    [*DeviceA-GigabitEthernet0/2/0] commit

    # Configure Device B.

    [~DeviceB] interface gigabitethernet 0/1/0
    [~DeviceB-GigabitEthernet0/1/0] clock synchronization enable
    [*DeviceB-GigabitEthernet0/1/0] clock priority 1
    [*DeviceB-GigabitEthernet0/1/0] commit
    [~DeviceB-GigabitEthernet0/1/0] quit
    [~DeviceB] interface gigabitethernet 0/2/0
    [~DeviceB-GigabitEthernet0/2/0] clock synchronization enable
    [*DeviceB-GigabitEthernet0/2/0] clock priority 2
    [*DeviceB-GigabitEthernet0/2/0] commit

    # # Configure Device D by using the same method for configuring Device B.

    # Configure Device C.

    [*DeviceC] clock bits-type bits0 2mhz
    [*DeviceC] clock source bits0 synchronization enable
    [*DeviceC] clock source bits0 priority 1
    [*DeviceC] clock source bits0 ssm sec
    [*DeviceC] commit
    [~DeviceC] quit
    [~DeviceC] interface gigabitethernet 0/1/0
    [~DeviceC-GigabitEthernet0/1/0] clock synchronization enable
    [*DeviceC-GigabitEthernet0/1/0] commit
    [~DeviceC-GigabitEthernet0/1/0] quit
    [~DeviceC] interface gigabitethernet 0/2/0
    [*DeviceC-GigabitEthernet0/2/0] clock synchronization enable
    [*DeviceC-GigabitEthernet0/2/0] clock priority 3
    [*DeviceC-GigabitEthernet0/2/0] commit

  3. Verify the configuration.

    Run the display clock source command on Device A, Device B, Device C, and Device D to check the clock synchronization configurations and clock source information.

    # Check the clock synchronization configurations and clock source information on Device A.

    <HUAWEI> display clock source
    System trace source State:   lock mode
                                  into pull-in range
     Current system trace source: bits0
     Current 2M-1 trace source:   system PLL
     Frequency lock success:      yes
    
     Master board
     Source        Pri(sys/2m-1)   In-SSM     Out-SSM    State      Ref-Source
     --------------------------------------------------------------------------
     bits0         1/---         ssua        --        normal     yes
     GE0/1/0            2/---         dnu        ssua       normal     yes
     GE0/2/0          ---/---         dnu        ssua       normal     yes
     

    # Check the clock synchronization configurations and clock source information on Device B.

    <HUAWEI> display clock source
    System trace source State:   lock mode
                                  into pull-in range
     Current system trace source: GigabitEthernet0/1/0
     Current 2M-1 trace source:   system PLL
     Frequency lock success:      yes
    
     Master board
     Source        Pri(sys/2m-1)   In-SSM     Out-SSM    State      Ref-Source
     --------------------------------------------------------------------------
     GE0/1/0          1/---         ssua        dnu       normal     yes
     GE0/2/0          2/---         ssua        ssua       normal     yes
     

    # Check the clock synchronization configurations and clock source information on Device C.

    <HUAWEI> display clock source
    System trace source State:   lock mode
                                  into pull-in range
     Current system trace source: GigabitEthernet0/2/0
     Current 2M-1 trace source:   system PLL
     Frequency lock success:      yes
    
     Master board
     Source        Pri(sys/2m-1)   In-SSM     Out-SSM    State      Ref-Source
     --------------------------------------------------------------------------
     bits0            1/---         sec        --       normal     yes
     GE0/1/0          ---/---       ssua        dnu       normal     yes
     GE0/2/0          3/---         ssua        ssua       normal     yes
     

    # Check the clock synchronization configurations and clock source information on Device D.

    <HUAWEI> display clock source
    System trace source State:   lock mode
                                  into pull-in range
     Current system trace source: GigabitEthernet0/2/0
     Current 2M-1 trace source:   system PLL
     Frequency lock success:      yes
    
     Master board
     Source        Pri(sys/2m-1)   In-SSM     Out-SSM    State      Ref-Source
     --------------------------------------------------------------------------
     GE0/1/0          1/---         dnu        ssua       normal     yes
     GE0/2/0          2/---         ssua        dnu       normal     yes

  4. Modify the clock type of the BITS0 on the Device A. Run the display clock source command on Device A, Device B, Device C, and Device D to check the clock synchronization configurations and clock source information.

    [*DeviceA] clock bits-type bits0 2mbps
    [*DeviceA] commit

    # Run the display clock source command on Device A. The command output shows that Device A has traced the clock signals sent from Device C.

    <HUAWEI> display clock source
    System trace source State:   lock mode
                                  into pull-in range
     Current system trace source: GigabitEthernet0/1/0
     Current 2M-1 trace source:   system PLL
     Frequency lock success:      yes
    
     Master board
     Source        Pri(sys/2m-1)   In-SSM     Out-SSM    State      Ref-Source
     --------------------------------------------------------------------------
     bits0      1/---         ssua        sec       abnormal     yes
     GE0/1/0          2/---           sec        dnu       normal     yes
     GE0/2/0          ---/---         sec        sec       normal     yes
     

    # Run the display clock source command on Device B. The command output shows that Device B has traced the clock signals sent from Device C.

    <HUAWEI> display clock source
    System trace source State:   lock mode
                                  into pull-in range
     Current system trace source: GigabitEthernet0/2/0
     Current 2M-1 trace source:   system PLL
     Frequency lock success:      yes
    
     Master board
     Source        Pri(sys/2m-1)   In-SSM     Out-SSM    State      Ref-Source
     --------------------------------------------------------------------------
     GE0/1/0          1/---         dnu        sec       normal     yes
     GE0/2/0          2/---         sec        dnu       normal     yes
     

    # Run the display clock source command on Device C. The command output shows that Device C has traced the clock signals sent from its connected BITS.

    <HUAWEI> display clock source
    System trace source State:   lock mode
                                  into pull-in range
     Current system trace source: bits0
     Current 2M-1 trace source:   system PLL
     Frequency lock success:      yes
    
     Master board
     Source        Pri(sys/2m-1)   In-SSM     Out-SSM    State      Ref-Source
     --------------------------------------------------------------------------
     bits0        1/---       sec        --        normal     yes
     GE0/1/0          ---/---       dnu        sec       normal     yes
     GE0/2/0          3/---         dnu        sec       normal     yes
     

    # Run the display clock source command on Device D. The command output shows that Device D has traced the clock signals sent from Device C.

    <HUAWEI> display clock source
    System trace source State:   lock mode
                                  into pull-in range
     Current system trace source: GigabitEthernet0/1/0
     Current 2M-1 trace source:   system PLL
     Frequency lock success:      yes
    
     Master board
     Source        Pri(sys/2m-1)   In-SSM     Out-SSM    State      Ref-Source
     --------------------------------------------------------------------------
     GE0/1/0          1/---         sec        dnu       normal     yes
     GE0/2/0          2/---         sec        sec       normal     yes
     

Configuration Files

  • Configuration file of Device A

    #
     sysname DeviceA
    #
    clock ssm-control on
    clock bits-type bits0 2mhz 
    clock source bits0 synchronization enable 
    clock source bits0 priority 1 
    clock source bits0 ssm ssua 
    #
    interface GigabitEthernet0/1/0
     clock synchronization enable
     clock priority 2
    #
    interface GigabitEthernet0/2/0
     clock synchronization enable
    #
    return 
  • Configuration file of Device B

    #
     sysname DeviceB
    #
    clock ssm-control on
    #
    interface GigabitEthernet0/1/0
     clock synchronization enable
     clock priority 1
    #
    interface GigabitEthernet0/2/0
     clock synchronization enable
     clock priority 2
    #
    return 
  • Configuration file of Device C

    #
     sysname DeviceC
    #
    clock ssm-control on
    clock bits-type bits0 2mhz 
    clock source bits0 synchronization enable 
    clock source bits0 priority 1 
    clock source bits0 ssm sec 
    #
    interface GigabitEthernet0/1/0
     clock synchronization enable
    #
    interface GigabitEthernet0/2/0
     clock synchronization enable
     clock priority 3
    #
    return 
  • Configuration file of Device D

    #
     sysname DeviceD
    #
    clock ssm-control on
    #
    interface GigabitEthernet0/1/0
     clock synchronization enable
     clock priority 1
    #
    interface GigabitEthernet0/2/0
     clock synchronization enable
     clock priority 2
    #
    return 
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Updated: 2019-01-02

Document ID: EDOC1100058392

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