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ME60 V800R010C10SPC500 Hardware Description

This is ME60 V800R010C10SPC500 Hardware Description
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Huawei uses machine translation combined with human proofreading to translate this document to different languages in order to help you better understand the content of this document. Note: Even the most advanced machine translation cannot match the quality of professional translators. Huawei shall not bear any responsibility for translation accuracy and it is recommended that you refer to the English document (a link for which has been provided).
Introduction to the Switching Network

Introduction to the Switching Network

This section describes the principle of the SFU.

The switching network responsible for exchanging data between BSUs is a key component of the ME60. The ME60 uses switching chips developed by Huawei and Memory-Crossbar-Memory (M-C-M) to provide a three-level switching mode. Level-1 and level-3 switching use a shared-memory model and are performed on BSUs; level-2 switching uses a Crossbar model and is performed on SFUs. Figure 10-18 shows the switching network of the ME60.

The level-1 switching chip on one BSU is fully connected to the level-2 switching chips on SFUs. The level-2 switching chips on the SFUs are also fully connected to the level-3 switching chip on another BSU. In addition, the level-2 crossbar switching chips work in load balancing mode on multiple switching planes. The entire switching network is unblocked. The following describes how data packets are transmitted across the switching network.

  1. Data packets enter an BSU through physical interfaces and are fragmented into cells of a fixed length. These cells are then sent to the level-1 switching chips. After being buffered and scheduled, the cells enter the crossbar switching chips on the SFU. The level-1 switching chip on an BSU is fully connected with all of the level-2 switching chips. As a result, the same number of cells can be distributed to each level-2 switching plane. This implements load balancing on switching planes and facilitates fault tolerance.

  2. After the cells reach the crossbar switching chips, the crossbar switching chips schedule the cells to the corresponding outbound interfaces according to the destination interfaces of the data packets. The cells are then sent to the level-3 switching chips on another BSU. At this time, the switching of the cells by the level-2 switching chips is completed.

  3. After the cells reach the level-3 switching chips on another BSU, the system searches for the destination interfaces. Once found, the cells are reassembled and sent out through physical interfaces. At this time, switching of the data packets is completed.

Figure 10-18 Switching network of the ME60

Reliability

The device has four SFUs that work in 3+1 load balancing mode. The four SFUs load balance services at the same time. When one SFU is faulty or being replaced, the other three SFUs automatically take over the services on the faulty one to prevent service interruption, thus improving system reliability.

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Updated: 2019-01-04

Document ID: EDOC1100059474

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