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S12700 V200R013C00 Command Reference

This document describes all the configuration commands of the device, including the command function, syntax, parameters, views, default level, usage guidelines, examples, and related commands.
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Clock Synchronization Commands

Clock Synchronization Commands

Command Support

Commands provided in this section and all the parameters in the commands are supported by all switch models by default, unless otherwise specified. For details, see specific commands.

clock 1pps-tod

Function

The clock 1pps-tod command sets the format of external 1PPS+ToD time signals.

The undo clock 1pps-tod command restores the default format of external 1PPS+ToD time signals.

By default, the format of external 1PPS+ToD time signals is RS232.

Format

clock 1pps-tod { rs232 | gps } [ chassis chassis-id ]

undo clock 1pps-tod [ chassis chassis-id ]

Parameters

Parameter

Description

Value

rs232

Indicates that the format of external 1PPS+ToD time signals is RS232.

-

gps

Indicates that the format of external 1PPS+ToD time signals is GPS.

-

chassis chassis-id

Specifies a chassis ID. This parameter is available only when the CSS function is enabled.

The value is 1 or 2.

Views

System view

Default Level

2: Configuration level

Usage Guidelines

1PPS+ToD time signals have two formats: RS232 and GPS. To set the format of external 1PPS+ToD time signals, run the clock 1pps-tod command.

If the time signal type is set to 1PPS+ToD using the clock bits-type command on the sender and receiver of time signals, ensure that the sender and receiver use the same 1PPS+ToD format (RS232 or GPS).

NOTE:

1PPS+ToD signals in the RS232 format and 1PPS+ToD in the GPS format are the same time type of different formats.

If the time signal type is set to 1pps-tod on the sender and receiver of time signals, set the same format of 1PPS+ToD (RS232 or GPS) on the sender and receiver.

Example

# Set the format of external 1PPS+ToD time signals to GPS.

<HUAWEI> system-view
[HUAWEI] clock 1pps-tod gps

clock bits-type

Function

The clock bits-type command sets the transmission mode of a BITS clock.

The undo clock bits-type command restores the default transmission mode of a BITS clock.

By default, a BITS clock works in bps-2m mode.

Format

clock bits-type { bps-2m | bps-1544m | hz-2m } { bits0 | bits1 } [ chassis chassis-id ]

clock bits-type { dcls-time | 1pps-tod } { in | out } { bits0 | bits1 } [ chassis chassis-id ]

undo clock bits-type { bps-2m | bps-1544m | hz-2m } { bits0 | bits1 } [ chassis chassis-id ]

undo clock bits-type { dcls-time | 1pps-tod } { in | out } { bits0 | bits1 } [ chassis chassis-id ]

undo clock bits-type { bits0 | bits1 }

Parameters

Parameter

Description

Value

bps-2m

Sets the transmission rate of the clock information from the external BITS clock to 2 Mbit/s.

-

bps-1544m

Sets the transmission rate of the clock information from the external BITS clock to 1.544 Mbit/s.

-

hz-2m

Sets the transmission frequency of the clock information from the external BITS clock to 2 MHz.

-

dcls-time

Sets the time of the external BITS clock to the DC Level Shifter (DCLS) time, which is an external time.

-

1pps-tod

Sets the time of the external BITS clock to 1 pps Time of Day (TOD), which is an external time.

-

in

Indicates that the external clock is the input clock, that is, synchronizes the time from the external clock to the local clock.

-

out

Indicates that the external clock is the output clock, that is, synchronizes the time from the local clock to the external clock.

-

bits0

Indicates the first BITS clock, BITS0.

-

bits1

Indicates the second BITS clock, BITS1.

-

chassis chassis-id

Specifies a chassis ID. This parameter is available only when the CSS function is enabled.

The value is 1 or 2.

Views

System view

Default Level

2: Configuration level

Usage Guidelines

To set the transmission mode of a BITS clock, run the clock bits-type command. The clock bits-type command is applicable only to clock synchronization and time synchronization through BITS interfaces.

The clock bits-type { bps-2m | bps-1544m | hz-2m } { bits0 | bits1 } [ chassis chassis-id ] command sets the clock mode.

The clock bits-type { dcls-time | 1pps-tod } { in | out } { bits0 | bits1 } [ chassis chassis-id ] command sets the time mode.

Precautions
  • In clock synchronization mode, the clock information is transmitted bidirectionally.

  • If the clock synchronization mode is set to BPS (bps-2m or bps-1544m) and if the quality level of the Synchronization Status Message (SSM) is used in clock source selection, the BITS clocks can obtain the quality level of the clock automatically. When the clock synchronization mode is set to other modes, such as hz-2m, the BITS clocks cannot obtain the SSM quality level. In this case, if quality level is required in clock source selection, you need to run the clock source source ssm { prc | ssua | ssub | sec | dnu } [ chassis chassis-id ] command to set the SSM quality level.

Example

# Configure the BITS0 interface to transmit clock information at a frequency of 2 MHz.

<HUAWEI> system-view
[HUAWEI] clock bits-type hz-2m bits0 
Related Topics

clock clear

Function

The clock clear command restores the automatic clock source selection mode.

Format

clock clear { bits1 | bits0 | system } [ chassis chassis-id ]

Parameters

Parameter

Description

Value

bits0

Indicates the BITS0 clock.

-

bits1

Indicates the BITS1 clock.

-

system

Indicates the system clock.

-

chassis chassis-id

Specifies a chassis ID. This parameter is available only when the CSS function is enabled.

The value is 1 or 2.

Views

System view

Default Level

2: Configuration level

Usage Guidelines

To clear configurations of the manual or forcible clock source selection mode and restore the automatic clock source selection mode, run the clock clear command.

Example

# Restore the automatic clock source selection mode.
<HUAWEI> system-view
[HUAWEI] clock clear system
Related Topics

clock ethernet-synchronization enable

Function

The clock ethernet-synchronization enable command enables synchronous Ethernet.

The undo clock ethernet-synchronization enable command disables synchronous Ethernet.

By default, synchronous Ethernet is not enabled.

Format

clock ethernet-synchronization enable

undo clock ethernet-synchronization enable

Parameters

None

Views

System view

Default Level

2: Configuration level

Usage Guidelines

To enable synchronous Ethernet, run the clock ethernet-synchronization enable command. After synchronous Ethernet is enabled on a switch, the switch selects the clock signal sent through Ethernet interfaces as the clock source.

The synchronous Ethernet function of an interface needs to be enabled both globally and on this interface. If the global synchronous Ethernet configuration is disabled, the synchronous Ethernet configuration on the interface is not deleted, but this function becomes unavailable.

Example

# Enable synchronous Ethernet on a switch.

<HUAWEI> system-view
[HUAWEI] clock ethernet-synchronization enable

clock extern-time out

Function

The clock extern-time out command configures a BITS interface as the sender of time signals, and sets the time type.

The undo clock extern-time out command deletes the configured time type.

By default, a BITS interface is not configured as the sender of time signals.

Format

clock extern-time out { dcls-time | 1pps-tod } [ chassis chassis-id ]

undo clock extern-time out [ chassis chassis-id ]

Parameters

Parameter

Description

Value

dcls-time

Sets the time of the external BITS clock to the DC Level Shifter (DCLS) time, which is an external time.

-

1pps-tod

Sets the time of the external BITS clock to 1 pps-tod, which is an external time.

-

chassis chassis-id

Specifies a chassis ID. This parameter is available only when the CSS function is enabled.

The value is 1 or 2.

Views

System view

Default Level

2: Configuration level

Usage Guidelines

This command is required only when the BITS interface needs to send the time signal.

Prerequisites

The type of the external time signals output by the BITS interface has been configured using the clock bits-type { dcls-time | 1pps-tod } { in | out } { bits0 | bits1 } [ chassis chassis-id ] command.

Example

# Set the type of the output time signal to 1pps-tod (GPS format).

<HUAWEI> system-view
[HUAWEI] clock extern-time out 1pps-tod

clock force-out-s1 (System view)

Function

The clock force-out-s1 command sets the synchronization status message code (S1 byte) sent by the BITS clock.

The undo clock force-out-s1 command cancels the setting of the S1 byte.

By default, the S1 byte is set automatically according to the SSM of the selected clock source.

Format

clock force-out-s1 { s1-prc | s1-ssu-t | s1-ssu-l | s1-sec | s1-dnu | else-s1-byte } { bits0 | bits1 } [ chassis chassis-id ]

undo clock force-out-s1 [ s1-prc | s1-ssu-t | s1-ssu-l | s1-sec | s1-dnu | else-s1-byte ] { bits0 | bits1 } [ chassis chassis-id ]

Parameters

Parameter

Description

Value

s1-prc

Sets the S1 byte for the stratum-1 clock.

0x2

s1-ssu-t

Sets the S1 byte for the stratum-2 clock.

0x4

s1-ssu-l

Sets the S1 byte for the stratum-3 clock.

0x8

s1-sec

Sets the S1 byte for the synchronous digital hierarchy (SDH) clock.

0xb

s1-dnu

Indicates not to use the S1 byte in clock syntonization.

0xf

else-s1-byte

Sets the S1 byte to other values.

The value is a hexadecimal number that ranges from 0 to FF.

bits0

Indicates the first BITS clock, BITS0.

-

bits1

Indicates the second BITS clock, BITS1.

-

chassis chassis-id

Specifies a chassis ID. This parameter is available only when the CSS function is enabled.

The value is 1 or 2.

Views

System view

Default Level

2: Configuration level

Usage Guidelines

Normally, the clock module sets the S1 byte according to the SSM level of the clock source.

NOTE:

This command is used for debugging and is not recommended in normal cases.

Example

# Set the S1 byte sent by the BITS0 clock to 11.

<HUAWEI> system-view
[HUAWEI] clock force-out-s1 11 bits0
Related Topics

clock force-out-s1 (interface view)

Function

The clock force-out-s1 command sets the synchronization status message code (S1 byte) sent by an interface.

The undo clock force-out-s1 command cancels the setting of the S1 byte.

By default, the S1 byte is set automatically according to the SSM level of the selected clock source.

Format

clock force-out-s1 { s1-prc | s1-ssu-t | s1-ssu-l | s1-sec | s1-dnu | else-s1-byte }

undo clock force-out-s1

Parameters

Parameter

Description

Value

s1-prc

Sets the S1 byte for the stratum-1 clock.

0x2

s1-ssu-t

Sets the S1 byte for the stratum-2 clock.

0x4

s1-ssu-l

Sets the S1 byte for the stratum-3 clock.

0x8

s1-sec

Sets the S1 byte for the SDH clock.

0xb

s1-dnu

Indicates not to use the S1 byte in clock syntonization.

0xf

else-s1-byte

Sets the S1 byte to other values.

The value is a hexadecimal number that ranges from 0 to FF.

Views

GE interface view, XGE interface view, 40GE interface view, 100GE interface view

Default Level

2: Configuration level

Usage Guidelines

Normally, the clock module sets the S1 byte according to the SSM level of the clock source.

NOTE:

This command is used in special networking and is not recommended in normal cases.

This command is invalid on a GE electrical interface.

Example

# Set the S1 byte sent by GigabitEthernet1/0/1 to 12.

<HUAWEI> system-view
[HUAWEI] interface gigabitethernet 1/0/1
[HUAWEI-GigabitEthernet1/0/1] clock force-out-s1 12
Related Topics

clock freq-deviation-detect enable

Function

The clock freq-deviation-detect enable command enables frequency offset check on clock signals.

The undo clock freq-deviation-detect enable command disables frequency offset check on clock signals.

By default, frequency offset check on clock signals is not enabled.

Format

clock freq-deviation-detect enable

undo clock freq-deviation-detect enable

Parameters

None

Views

System view

Default Level

2: Configuration level

Usage Guidelines

If the clock synchronization network has high requirements for frequency offset of clock signals, run the clock freq-deviation-detect enable command to enable frequency offset check. After this function is enabled, the system performs frequency offset check on clock signals. If the frequency offset value exceeds the specified threshold, the system considers that the clock source is unreliable and triggers another automatic clock source selection.

Frequency offset check on a clock source helps determine whether the quality of the clock source is good or not. If the frequency offset value of a clock source exceeds the specified threshold, the system clock does not trace this clock source any more. To configure the range of frequency offset check, run the clock freq-deviation-detect-range left-range right-range command.

Example

# Enable frequency offset check on clock signals.

<HUAWEI> system-view
[HUAWEI] clock freq-deviation-detect enable

clock freq-deviation-detect-range

Function

The clock freq-deviation-detect-range command configures the range of frequency offset check.

The undo clock freq-deviation-detect-range command restores the default range of frequency offset check.

By default, the frequency offset value ranges from -9.2 ppm to 9.2 ppm.

Format

clock freq-deviation-detect-range left-range right-range

undo clock freq-deviation-detect-range

Parameters

Parameter

Description

Value

left-range

Specifies the minimum frequency offset value.

The value is an integer that ranges from 50 to 1000.

The unit is -0.01 ppm.

The default value is -9.2 ppm.

right-range

Specifies the maximum frequency offset value.

The value is an integer that ranges from 50 to 1000.

The unit is 0.01 ppm.

The default value is 9.2 ppm.

Views

System view

Default Level

2: Configuration level

Usage Guidelines

If the frequency offset value of a clock source is out of the range, the clock source has a too large frequency offset. To configure the range of frequency offset check, run the clock freq-deviation-detect-range command.

NOTE:

Do not change the range of frequency offset check.

Example

# Configure the range of frequency offset check.

<HUAWEI> system-view
[HUAWEI] clock freq-deviation-detect-range 50 600

clock hold-for-ever

Function

Using the clock hold-for-ever command, you can configure the clock module to hold the previous clock information permanently when all the clock sources are lost.

Using the undo clock hold-for-ever command, you can restore the default holding mode, that is, the 24-hour holding mode.

By default, the clock module holds the previous clock information for 24 hours when all the clock sources are lost.

Format

clock hold-for-ever

undo clock hold-for-ever

Parameters

None

Views

System view

Default Level

2: Configuration level

Usage Guidelines

When all the clock sources are lost, the clock module enters the holding state and retains the original frequency offset according to the clock information traced before.

In the 24-hour holding mode, the clock module enters the free running mode not more than 24 hours after all the clock sources are lost. In the free running mode, the clock module uses the clock signal generated by the local oscillator as the clock source.

Example

# Configure the permanent holding mode for the clock module.

<HUAWEI> system-view
[HUAWEI] clock hold-for-ever
Related Topics

clock id

Function

The clock id command sets the ID of a clock source.

The undo clock id command restores the default ID of a clock source.

The default ID of a clock source is 0.

Format

clock id id source source [ chassis chassis-id ]

undo clock id [ id ] source source [ chassis chassis-id ]

Parameters

Parameter

Description

Value

id

Specifies the ID of a clock source.

The value is an integer that ranges from 0 to 15. By default, the ID of a clock source is 0.

source source

Specifies the number of a clock source..

The value is an integer that ranges from 0 to 8. The mappings between the clock source numbers and clock sources are as follows:
  • 0: Inner Clock, which is the clock generated by the local oscillator and cannot be changed
  • 1: BITS0, which is the BITS0 clock
  • 2: BITS1, which is the BITS1 clock
  • 3: Slave board BITS0, which is the BITS0 clock on the slave board
  • 4: Slave board BITS1, which is the BITS1 clock on the slave board
  • 5: Left-frame clock, which is the clock signal sent from the left side of the frame
  • 6: Right-frame clock, which is the clock signal sent from the right side of the frame
  • 7: FSU, which is the clock on the FSU
  • 8: Slave board FSU, which is the clock on the peer FSU
chassis chassis-id

Specifies a chassis ID. This parameter is available only when the CSS function is enabled.

The value is 1 or 2.

Views

System view

Default Level

2: Configuration level

Usage Guidelines

To prevent timing loops on a ring network consisting of multiple devices, run the clock id command command to set the ID of a clock source. The ID of the clock source can be used only in extended mode where the SSM quality level is used in clock source selection. If the system selects a clock source, the higher four bits of the S1 byte sent by the system are occupied by the ID of the clock source.

  • When the local device receives the S1 byte with the ID of its own clock source, it indicates that the device receives the clock source of its own. That is, a timing loop occurs. Then the quality level of the received clock source is set to DNU so that it is not involved in clock source selection. In this manner, timing loops are prevented.
  • If the local device receives an S1 byte without the ID of the clock source, it indicates that the clock source is from another device and can be used as the reference clock source. The S1 byte is then transmitted among devices to select the clock source.

The ID of a clock source occupies only the right-most four bits of the S1 byte; therefore, only 16 IDs ranging from 0 to 15 can be used. If multiple ring networks exist, the 16 IDs are not enough.

To solve the problem of insufficient IDs, you can specify an ID that is not used on the local ring network for the clock sources on another ring network on the intersection point of the two ring networks. In this manner, IDs of different ring networks are isolated, and the same ID can be used by different networks.

NOTE:

The ID of the clock source is used to prevent timing loops. If a ring network consists of the device and other types of devices, it is recommended that you set the ID only for the inner clock generated by the crystal oscillator because the clocks of the device and another type of device may not match.

Example

# Set the ID of a clock source.

<HUAWEI> system-view
[HUAWEI] clock id 1 source 1

clock lockout

Function

The clock lockout command locks a clock source to disable it from participating in clock source selection.

The undo clock lockout command unlocks a clock source to enable it to participate in clock source selection.

By default, all clock sources participate in clock source selection.

Format

clock lockout source source { system | bits0 | bits1 } [ chassis chassis-id ]

undo clock lockout source source { system | bits0 | bits1 } [ chassis chassis-id ]

Parameters

Parameter

Description

Value

source source

Specifies the number of a clock source.

The value is an integer that ranges from 0 to 8 for the clock source of the system clock and 5 to 9 for the clock source of the BITS clock.

The mappings between the clock source numbers and clock sources are as follows:

  • 0: Inner Clock, that is, the clock generated by the local oscillator, which cannot be changed
  • 1: BITS0, that is, the BITS0 clock
  • 2: BITS1, that is, the BITS1 clock
  • 3: Slave Board BITS0, that is, the BITS0 clock on the slave board
  • 4: Slave Board BITS1, that is, the BITS1 clock on the slave board
  • 5: Left Frame Clock, that is, the clock signal sent from the left side of the frame
  • 6: Right Frame Clock, that is, the clock signal sent from the right side of the frame
  • 7: FSU, that is, the clock on the FSU
  • 8: Slave Board FSU, that is, the clock on the peer FSU
  • 9: System Clock, that is, the clock selected automatically or specified by forcible switchover or manual switchover

system

Locks a clock source of the system clock.

-

bits0

Locks a clock source of the BITS0 clock.

-

bits1

Locks a clock source of the BITS1 clock.

-

chassis chassis-id

Specifies a chassis ID. This parameter is available only when the CSS function is enabled.

The value is 1 or 2.

Views

System view

Default Level

2: Configuration level

Usage Guidelines

Clock source 0 (inner clock) and clock source 9 (system clock) cannot be locked.

If you run the undo clock source priority command to delete the priority of a clock source, the locking state of the clock source is cancelled.

Locking a clock source fails in any of the following conditions:

  • The number of the clock source to be locked for the system clock is out of the range 0-8.

  • The number of the clock source to be locked for the BITS clock is out of the range 5-9.

  • The clock source to be locked is the inner clock or system clock.

  • The priority of the clock source to be locked is not set and the clock source uses the default priority 255.

Example

# Lock the clock source sent from the left side of the frame (clock source 5).

<HUAWEI> system-view
[HUAWEI] clock lockout source 5 system
Related Topics

clock map unk

Function

The clock map unk command maps a clock source with the SSM quality level of UNK to a new SSM quality level.

The undo clock map unk command cancels the mapping between the clock source with the SSM quality level of UNK to a new SSM quality level.

By default, the SSM quality level is UNK.

Format

clock map unk { prc | ssua | ssub | sec }

undo clock map unk

Parameters

Parameter Description Value
prc Indicates G.811 clock signals with the SSM quality level of PRC. -
ssua Indicates G.812 transit node clock signals with the SSM quality level of SSUA. -
ssub Indicates G.812 local node clock signals with the SSM quality level of SSUB. -
sec Indicates SDH clock source signals with the SSM quality level of SEC. -

Views

System view

Default Level

2: Configuration level

Usage Guidelines

If the SSM quality level of an upstream clock source is UNK, to allow switches to trace this clock source, run the clock map unk command to map the upstream clock source to a new SSM quality level. By default, a clock source with the SSM quality level of UNK is mapped to the SSM quality level of DNU. In this case, if SSM control is enabled also, the clock source does not participate in clock source selection.

By default, when SSM control is enabled, the clock source with the SSM quality level of UNK does not participate in clock source selection.

Example

# Map the clock source with the SSM quality level of UNK to the SSM quality level of PRC.

<HUAWEI> system-view
[HUAWEI] clock map unk prc

clock no-id-out (System view)

Function

The clock no-id-out command disables a clock from sending the clock source ID.

The undo clock no-id-out command enables a clock to send the clock source ID.

By default, a clock sends the clock source ID.

Format

clock no-id-out { bits0 | bits1 } [ chassis chassis-id ]

undo clock no-id-out { bits0 | bits1 } [ chassis chassis-id ]

Parameters

Parameter

Description

Value

bits0

Indicates the first BITS clock, BITS0.

-

bits1

Indicates the second BITS clock, BITS1.

-

chassis chassis-id

Specifies a chassis ID. This parameter is available only when the CSS function is enabled.

The value is 1 or 2.

Views

System view

Default Level

2: Configuration level

Usage Guidelines

After you run the clock no-id-out command, the right-most four bits of the S1 byte are set to 0 when the extended SSM mode is used.

You can run the display clock command to view the configuration result.

Example

# Disable the BITS0 clock from sending the clock source ID.

<HUAWEI> system-view
[HUAWEI] clock no-id-out bits0 
Related Topics

clock no-id-out (interface view)

Function

Using the clock no-id-out command, you can disable an interface from sending the clock source ID.

Using the undo clock no-id-out command, you can enable an interface to send the clock source ID.

By default, an interface sends the clock source ID.

Format

clock no-id-out

undo clock no-id-out

Parameters

None

Views

GE interface view, XGE interface view, 40GE interface view, 100GE interface view

Default Level

2: Configuration level

Usage Guidelines

After you run the clock no-id-out command, the higher four bits of the S1 byte are set to 0 when the extended SSM mode is used.

You can run the display clock state command to query the configuration result.

NOTE:

This command is invalid on a GE electrical interface.

Example

# Disable GigabitEthernet1/0/0 from sending the clock source ID.

<HUAWEI> system-view
[HUAWEI] interface gigabitethernet 1/0/0
[HUAWEI-GigabitEthernet1/0/0] clock no-id-out
Related Topics

clock priority (interface view)

Function

The clock priority command sets the priority of a clock source.

The undo clock priority command restores the default priority of a clock source.

By default, the priority of a clock source is 255.

Format

clock priority priority-value

undo clock priority

Parameters

Parameter Description Value
priority-value Specifies the priority of a clock source. The value is an integer that ranges from 0 to 253. A smaller value indicates a higher priority.

Views

Interface view

Default Level

2: Configuration level

Usage Guidelines

By default, the priority of a clock source is 255, indicating that the clock source does not participate in clock source selection.

In automatic clock source selection mode, a clock source can participate in clock source selection only when a priority is configured. In manual and forcible clock source selection modes, clock source switching can be performed regardless of the clock source priority. In this case, whether a priority is configured does not affect the switching result. To set the priority of a clock source, run the clock priority command.

Example

# Set the priority of the clock source on the interface XGE1/0/1 to 10.

<HUAWEI> system-view
[HUAWEI] interface xgigabitethernet 1/0/1
[HUAWEI-XGigabitEthernet1/0/1] clock priority 10

clock source priority (system view)

Function

The clock source priority command sets the priority of a clock source.

The undo clock source priority command restores the default priority of a clock source.

By default, the priority of an internal clock source and a system clock source is 254, and the priority of other clock sources is 255.

Format

clock source source priority priority { system | bits0 | bits1 } [ chassis chassis-id ]

undo clock source source priority [ priority ] { system | bits0 | bits1 } [ chassis chassis-id ]

Parameters

Parameter

Description

Value

source source

Specifies a clock source.

source: specifies the ID of the clock source.

The value is an integer that ranges from 0 to 9.

The value ranges from 0 to 8 for a system clock source.

The value ranges from 5 to 9 for a BITS clock source.

The mappings between the clock source numbers and clock sources are as follows:

  • 0: internal clock, which is the clock generated by the internal oscillator and cannot be changed
  • 1: BITS0
  • 2: BITS1
  • 3: slave board BITS0
  • 4: slave board BITS1
  • 5: left-frame clock
  • 6: right-frame clock
  • 7: FSU
  • 8: slave board FSU
  • 9: system clock, which is the external clock manually or forcibly specified or automatically selected

priority priority

Specifies the priority of a clock source.

The value is an integer that ranges from 0 to 253.

By default, the priority of an internal clock source and a system clock source is 254, and the priority of other clock sources is 255.

A smaller value indicates a higher priority.

system

Indicates the system clock.

-

bits0

Indicates the BITS0 clock.

-

bits1

Indicates the BITS1 clock.

-

chassis chassis-id

Specifies a chassis ID. This parameter is available only when the CSS function is enabled.

The value is 1 or 2.

Views

System view

Default Level

2: Configuration level

Usage Guidelines

When PTP is enabled and the PTP clock is a slave clock, the frequency of the PTP clock can be used as a line clock to participate in clock source selection.

In automatic clock source selection mode, a clock source can participate in clock source selection only when a priority is configured. In manual and forcible clock source selection modes, clock source switching can be performed regardless of the clock source priority. In this case, whether a priority is configured does not affect the switching result. To set the priority of a clock source, run the clock source priority command.

Example

# Set the priority of clock source 1 to 11.
<HUAWEI> system-view
[HUAWEI] clock source 1 priority 11 system

clock recv-sa-bit | clock send-sa-bit

Function

The clock recv-sa-bit command specifies the SA bit field from which the SDH synchronization information code (S1 byte) is received.

The undo clock recv-sa-bit command restores the default setting that the S1 byte is received by the SA4 bit field.

The clock send-sa-bit command specifies the SA bit field that is used to send the S1 byte.

The undo clock send-sa-bit command restores the default setting that the S1 byte is sent by the SA4 bit field.

By default, the S1 byte is transmitted in the SA4 bit field.

Format

clock recv-sa-bit { sa4 | sa5 | sa6 | sa7 | sa8 } { bits0 | bits1 } [ chassis chassis-id ]

undo clock recv-sa-bit { sa4 | sa5 | sa6 | sa7 | sa8 } { bits0 | bits1 } [ chassis chassis-id ]

clock send-sa-bit { sa4 | sa5 | sa6 | sa7 | sa8 } { bits0 | bits1 } [ chassis chassis-id ]

undo clock send-sa-bit { sa4 | sa5 | sa6 | sa7 | sa8 } { bits0 | bits1 } [ chassis chassis-id ]

Parameters

Parameter

Description

Value

sa4

Uses the SA4 bit field to transmit the S1 byte.

-

sa5

Uses the SA5 bit field to transmit the S1 byte.

-

sa6

Uses the SA6 bit field to transmit the S1 byte.

-

sa7

Uses the SA7 bit field to transmit the S1 byte.

-

sa8

Uses the SA8 bit field to transmit the S1 byte.

-

bits0

Indicates the first BITS clock, BITS0.

-

bits1

Indicates the second BITS clock, BITS1.

-

chassis chassis-id

Specifies a chassis ID. This parameter is available only when the CSS function is enabled.

The value is 1 or 2.

Views

System view

Default Level

2: Configuration level

Usage Guidelines

A multiframe transmitted between BITS interfaces consists of eight sub-multiframes. Each frame contains five spare bits: SA4 bit to SA8 bit. You can select any one of the spare SA bits to transmit the SDH synchronization code (S1 byte). The eight frames jointly carry the eight bits of the S1 byte.

If sender and receiver are both Ethernet clock synchronization devices, you do not need to run the clock recv-sa-bit or clock send-sa-bit command because the Ethernet clock synchronization devices can identify the S1 byte no matter which bit transmits it. The commands are used when an Ethernet clock synchronization device synchronizes the clock with another type of device through the BITS interface. In this case, you need to specify the same bit that transmits the S1 byte on both ends to ensure that both ends can identify the S1 byte.

Example

# Configure the BITS0 clock to receive the S1 byte from the SA5 bit field.

<HUAWEI> system-view
[HUAWEI] clock recv-sa-bit sa5 bits0

# Configure the BITS0 clock to send the S1 byte by using the SA8 bit field.

<HUAWEI> system-view
[HUAWEI] clock send-sa-bit sa8 bits0
Related Topics

clock source

Function

The clock source command sets the clock source selection mode to manual or forcible and specifies the master clock source.

The undo clock source command restores the default clock source selection mode.

By default, the automatic clock source selection mode is used.

Format

clock { manual | force } source source { system | bits0 | bits1 } [ chassis chassis-id ]

undo clock { manual | force } source source { system | bits0 | bits1 } [ chassis chassis-id ]

Parameters

Parameter

Description

Value

manual Indicates that the manual clock source selection mode is used. -
force Indicates that the forcible clock source selection mode is used. -

source source

Specifies the number of a clock source.

The value is an integer that ranges from 0 to 8 for a system clock and from 5 to 9 for a BITS clock.

The mappings between the clock source numbers and clock sources are as follows:

  • 0: internal clock, which is the clock generated by the internal oscillator and cannot be changed
  • 1: BITS0
  • 2: BITS1
  • 3: slave board BITS0
  • 4: slave board BITS1
  • 5: left-frame clock
  • 6: right-frame clock
  • 7: FSU
  • 8: slave board FSU
  • 9: system clock, which is the external clock manually or forcibly specified or automatically selected

system

Indicates the system clock.

-

bits0

Indicates the BITS0 clock.

-

bits1

Indicates the BITS1 clock.

-

chassis chassis-id

Specifies a chassis ID. This parameter is available only when the CSS function is enabled.

The value is 1 or 2.

Views

System view

Default Level

2: Configuration level

Usage Guidelines

To configure the clock source selection mode as manual or forcible, run the clock source command. In manual clock source selection mode, a clock source can be switched to a clock source with a higher SSM quality level, regardless of the clock source priority. In forcible clock source selection mode, a clock can be selected regardless of the SSM quality level and priority.

Precautions
NOTE:

Manual clock source switching fails in any of the following conditions:

  • The clock source signals are invalid.

  • The priority of the clock source is reset to DIS (255) using the undo clock source priority command.

  • The clock source is locked using the clock lockout command.

  • A system clock with the ID ranging from 0 to 8 cannot be switched to another clock source.

  • A BITS clock with the ID ranging from 5 to 9 cannot be switched to another clock source.

  • A clock source with the SSM quality level of DNU or lower cannot be switched.

  • A clock source cannot be switched to another one with a lower SSM quality level.

If a clock source in manual clock source selection mode does not meet conditions, the clock source automatically switches to the automatic clock source selection mode. If a clock source in forcible clock source selection mode does not meet conditions, for example, the clock source is abnormal, the clock source automatically switches to the hold mode. After the clock source is restored, it is automatically selected again.

A manually selected clock source is used temporarily and no configuration file is generated. To permanently use a clock source, use the forcible clock source selection mode.

The latest configuration of manual clock source selection overrides the previous configuration of manual clock source selection but not forcible clock source selection. The latest configuration of forcible clock source selection overrides the previous configuration of manual or forcible clock source selection.

Example

# Manually switch the BITS0 clock to the locked clock source 8.
<HUAWEI> system-view
[HUAWEI] clock manual source 8 bits0

clock source-lost holdoff-time

Function

The clock source-lost holdoff-time command configures the holdoff time for the system to consider a clock source lost.

The undo clock source-lost holdoff-time command restores the holdoff time for the system to consider a clock source lost.

By default, the holdoff time for the system to consider a clock source lost is 500 ms.

Format

clock source-lost holdoff-time value source source [ chassis chassis-id ]

undo clock source-lost holdoff-time [ value ] source source [ chassis chassis-id ]

Parameters

Parameter

Description

Value

value

Specifies the holdoff time for the system to consider a clock source lost.

The value is an integer that ranges from 3 to 18, in 100 milliseconds.

source source

Specifies the number of a clock source.

The value is an integer that ranges from 0 to 8.

The mappings between the clock source numbers and clock sources are as follows:

  • 0: internal clock, which is the clock generated by the internal oscillator and cannot be changed
  • 1: BITS0
  • 2: BITS1
  • 3: slave board BITS0
  • 4: slave board BITS1
  • 5: left-frame Clock
  • 6: right-frame Clock
  • 7: FSU
  • 8: slave board FSU
chassis chassis-id

Specifies a chassis ID. This parameter is available only when the CSS function is enabled.

The value is 1 or 2.

Views

System view

Default Level

2: Configuration level

Usage Guidelines

The system considers a clock source lost after a specified holdoff time. Within this period, the system considers that the clock source exists. Setting the holdoff time can avoid some mistakes in determining the clock source caused by occasional signal jitter on the network. To set the holdoff time for the system to consider a clock source lost, run the clock source-lost holdoff-time command.

If clock source switching needs to be implemented as soon as possible, set holdoff-time to a small value. To prevent frequent clock source switching, set holdoff-time to a large value.

Example

# Set the holdoff time for the system to consider a clock source lost to 400 ms.

<HUAWEI> system-view
[HUAWEI] clock source-lost holdoff-time 4 source 1

clock source ssm (system view)

Function

The clock source ssm command configures the SSM quality level of a clock source.

The undo clock source ssm command restores the default SSM quality level of a clock source.

By default, the SSM quality level of clock source 0 or 9 is SEC, and that of other clock sources is DNU.

Format

clock source source ssm { prc | ssua | ssub | sec | dnu } [ chassis chassis-id ]

undo clock source source ssm [ chassis chassis-id ]

Parameters

Parameter Description Value
dnu Indicates that the clock source is unavailable. -
prc Indicates G.811 clock signals with the SSM quality level of PRC. -
sec Indicates SDH clock source signals with the SSM quality level of SEC. -
ssua Indicates G.812 transit node clock signals with the SSM quality level of SSUA. -
ssub Indicates G.812 local node clock signals with the SSM quality level of SSUB. -
source source

Specifies a clock source.

source: specifies the ID of the clock source.

The value is an integer that ranges from 0 to 8.

The mappings between the clock source numbers and clock sources are as follows:

  • 0: internal clock, which is the clock generated by the internal oscillator and cannot be changed
  • 1: BITS0
  • 2: BITS1
  • 3: slave board BITS0
  • 4: slave board BITS1
  • 5: left-frame clock
  • 6: right-frame clock
  • 7: FSU
  • 8: slave board FSU
  • 9: system clock, which is the external clock manually or forcibly specified or automatically selected
chassis chassis-id

Specifies a chassis ID. This parameter is available only when the CSS function is enabled.

The value is 1 or 2.

Views

System view

Default Level

2: Configuration level

Usage Guidelines

When SSM control is enabled using the clock ssm-control on command, an SSM quality level needs to be specified for the clock source on an interface. To set the SSM quality level of a clock source, run the clock source ssm command.

Example

# Set the SSM quality level of a clock source to PRC.

<HUAWEI> system-view
[HUAWEI] clock source 2 ssm prc

clock ssm-control

Function

The clock ssm-control command enables or disables SSM quality levels are used for automatic clock source selection..

By default, SSM quality levels are not used for clock source selection.

Format

clock ssm-control { on [ extend ] | off }

Parameters

Parameter Description Value
on Enables SSM control. -
off Disables SSM control. -
extend Indicates the extended SSM mode in which the clock source ID can be sent in the right-most four bits of the S1 byte in an SSM message. -

Views

System view

Default Level

2: Configuration level

Usage Guidelines

When the system clock works in automatic clock source selection mode, if SSM control is enabled, the system clock selects the clock source to trace based on SSM quality levels and then the priorities. If SSM control is disabled, the system clock selects the clock source to trace based on priorities. To configure SSM control, run the clock ssm-control command.

Example

# Enable SSM control.

<HUAWEI> system-view
[HUAWEI] clock ssm-control on

clock switch

Function

The clock switch command configures the recovery mode of a clock node.

By default, clock nodes work in revertive mode.

Format

clock switch { revertive | non-revertive }

Parameters

Parameter Description Value
revertive Indicates the revertive mode. -
non-revertive Indicates the non-revertive mode. -

Views

System view

Default Level

2: Configuration level

Usage Guidelines

To configure a clock source to work in revertive or non-revertive mode, run the clock switch command.
  • Revertive mode: If the SSM quality level is used for clock source selection, the device automatically performs switching once a better clock source is determined based on the SSM quality levels and priorities. If the SSM quality level is not used for clock source selection, the device automatically performs switching once a better clock source is determined based on the priorities.
  • Non-revertive mode: If the priority of the current clock source is 255, the clock source has been locked using the clock lockout command, or the clock source is invalid, clock source selection needs to be performed again. During re-selection of a clock source, if the SSM quality level is used to select a clock source, the clock source is selected based on the SSM quality level and priority. If SSM quality levels are not configured to participate in clock source selection, a clock source is selected based on priorities.

Example

# Configure a clock node to work in revertive mode.

<HUAWEI> system-view
[HUAWEI] clock switch revertive

clock synchronization enable

Function

The clock synchronization enable command enables clock synchronization.

The undo clock synchronization enable command disables clock synchronization.

By default, clock synchronization is not enabled.

Format

clock synchronization enable

undo clock synchronization enable

Parameters

None

Views

Interface view

Default Level

2: Configuration level

Usage Guidelines

An interface can participate in clock source selection only after clock synchronization is enabled.

Example

# Enable clock synchronization on the interface XGE1/0/1.

<HUAWEI> system-view
[HUAWEI] interface xgigabitethernet 1/0/1
[HUAWEI-XGigabitEthernet1/0/1] clock synchronization enable

clock source ptp synchronization enable

Function

The clock source ptp synchronization enable command enables clock synchronization of a PTP clock source.

The undo clock source ptp synchronization enable command disables clock synchronization from a PTP clock source.

By default, clock synchronization is not enabled for a PTP clock source.

Format

clock source ptp synchronization enable

undo clock source ptp synchronization enable

Parameters

None

Views

System view

Default Level

2: Configuration level

Usage Guidelines

To enable clock synchronization for a PTP clock source, run the clock source ptp synchronization enable command. If a PTP clock source with clock synchronization enabled is selected as the clock source, frequency is transmitted through PTP messages.

An interface can participate in clock source selection after it is enabled with clock synchronization using the clock synchronization enable command.

Example

# Enable clock synchronization for a PTP clock source.

<HUAWEI> system-view
[HUAWEI] clock source ptp synchronization enable

clock wtr

Function

The clock wtr command sets the wait-to-restore (WTR) time for a clock source.

The undo clock wtr command restores the default WTR time.

By default, the WTR time of a clock source is 1 minute.

Format

clock wtr wtr-time source source [ chassis chassis-id ]

undo clock wtr wtr-time [ wtr-time ] source source [ chassis chassis-id ]

Parameters

Parameter

Description

Value

wtr-time

Specifies the WTR time of a clock source.

The value is an integer that ranges from 0 to 12. The unit is minute.

source source

Specifies a clock source.

source: specifies the ID of the clock source.

The value is an integer that ranges from 0 to 8.

The mappings between the clock source numbers and clock sources are as follows:

  • 0: internal clock, which is the clock generated by the internal oscillator and cannot be changed
  • 1: BITS0
  • 2: BITS1
  • 3: slave board BITS0
  • 4: slave board BITS1
  • 5: left-frame clock
  • 6: right-frame clock
  • 7: FSU
  • 8: slave board FSU
NOTE:

If source is set to 5, this command sets the WTR time for the left-frame clock. The WTR time does not take effect for clock switching between ports in the same half frame. In networking application, if multiple line clock sources exist, they should be distributed in different half frames.

chassis chassis-id

Specifies a chassis ID. This parameter is available only when the CSS function is enabled.

The value is 1 or 2.

Views

System view

Default Level

2: Configuration level

Usage Guidelines

When a lost clock source is restored, the system waits for a period of 0 to 12 minutes before considering the clock source available. During this period, the system considers the clock source lost.

Setting the WTR time can avoid some mistakes in determining the clock source caused by occasional signal jitter on the network.

The default WTR time of a clock source is 1 minute. Generally, you do not need to change the default value. If you want to view the clock source switching result during debugging, set the WTR time to 0.

Example

# Set the WTR time to 0.

<HUAWEI> system-view
[HUAWEI] clock wtr 0 source 1

display clock

Function

The display clock command displays the configuration of a BITS clock.

Format

display clock { bits0 | bits1 } [ slave ] [ chassis chassis-id ]

Parameters

Parameter

Description

Value

bits0

Indicates the BITS0 clock on the master clock board.

-

bits1

Indicates the BITS1 clock on the master clock board.

-

slave

Indicates a BITS clock on the slave clock board.

-

chassis chassis-id

Specifies a chassis ID. This parameter is available only when the CSS function is enabled.

The value is 1 or 2.

Views

All views

Default Level

1: Monitoring level

Usage Guidelines

After you run the clock bits-type, clock recv-sa-bit | clock send-sa-bit, or clock force-out-s1 (System view) command and so on to configure a BITS clock, you can run the display clock command to check the configuration result.

Example

# Display information about the BITS0 clock.

<HUAWEI> display clock bits0
Direction: out.
Type: 1pps.
Recv sa-bit: SA5.
Send sa-bit: SA8.
Force out s1: Yes, The s1 byte configed is:0x11.
ID out: Yes

# Display information about the BITS1 clock.

<HUAWEI> display clock bits1
Type: 2M bps.
Recv sa-bit: SA4.
Send sa-bit: SA4.
Recv s1 byte: 0x0f.
Send s1 byte: 0x12.
Force out s1: No
ID out: Yes       
Table 3-204  Description of the display clock command output

Item

Description

Direction

Transmission direction of the BITS clock signal, which can be in or out. If the BITS clock works in clock synchronization mode, namely, 2 Mbps, 1.544 Mbps, or 2 MHz mode, this field is meaningless.

Type

Mode of the BITS clock.

Recv sa-bit

SA bit from which the S1 byte is received.

Send sa-bit

SA bit through which the S1 byte is sent.

Recv s1-bit

Value of the S1 byte received from the LPU.

Send s1-bit

Value of the S1 byte sent by the BITS clock. The value can be obtained from the SSM quality level of the clock source selected by the BITS clock or set by the clock send-sa-bit command.

Force out s1

S1 byte that is set forcibly.

ID out

Whether the ID of the BITS clock is contained in the S1 byte.

display clock description

Function

Using the display clock description command, you can view the meaning of each clock source number.

Format

display clock description

Parameters

None

Views

All views

Default Level

1: Monitoring level

Usage Guidelines

This command displays all the clock sources supported by the device.

NOTE:

Clock sources 7 and 8 are reserved and not supported by the device currently.

Example

# Display the description of clock sources.

<HUAWEI> display clock description
Reference           Clock-source                                                
---------------------------------------------------------------------           
0                   Inner Clock                                                 
1                   BITS0                                                       
2                   BITS1                                                       
3                   Slave Board BITS0                                           
4                   Slave Board BITS1                                           
5                   Left Frame Clock                                            
6                   Right Frame Clock                                           
7                   FSU                                                         
8                   Slave Board FSU                                             
9                   System Clock                                                
10                  Peer System Clock                                           
Table 3-205  Description of the display clock description command output

Item

Description

Reference

Number of a clock source.

Clock-source

Name of a clock source.

display clock freq-deviation-detect-range

Function

The display clock freq-deviation-detect-range command displays the configured range of frequency offset check.

Format

display clock freq-deviation-detect-range

Parameters

None

Views

All views

Default Level

1: Monitoring level

Usage Guidelines

After the range of frequency offset check is set using the clock freq-deviation-detect-range command, run the display clock freq-deviation-detect-range command to view the configuration.

Example

# Display the range of frequency offset check.

<HUAWEI> display clock freq-deviation-detect-range
Info: The clock frequency check range is [-0.50 ppm, 6.00 ppm].
Table 3-206  Description of the display clock freq-deviation-detect-range command output

Item

Description

Clock frequency check range

Range of frequency offset check

display clock freq-deviation-detect-result

Function

The display clock freq-deviation-detect-result command displays the frequency offset check result of a clock source.

Format

display clock freq-deviation-detect-result [ chassis chassis-id ]

Parameters

Parameter

Description

Value

chassis chassis-id

Specifies a chassis ID. This parameter is available only when the CSS function is enabled.

The value is 1 or 2.

Views

All views

Default Level

1: Monitoring level

Usage Guidelines

By default, the check result of frequency offset does not affect clock source selection. After the clock freq-deviation-detect enable command is run, the system selects a clock source according to the check result of frequency offset. The clock source whose frequency offset is out of the range is tagged "signal-fail."

NOTE:
  • The system does not check the frequency offset of the clock source tagged "signal-fail."
  • The system does not check the frequency offset of an internal clock.

Example

# Display the check result of frequency offset.

<HUAWEI> display clock freq-deviation-detect-result
Reference      Clock Source                  Freq-Check-Result(Unit:ppm)                                                            
---------------------------------------------------------------------                                                               
0              Inner Clock                   ---                                                                                    
1              BITS0                         Unchecked                                                                              
2              BITS1                         Unchecked                                                                              
3              Slave Board BITS0             Unchecked                                                                              
4              Slave Board BITS1             Unchecked                                                                              
5              Left Frame Clock              Unchecked                                                                              
6              Right Frame Clock             Unchecked                                                                              
7              FSU                           Unchecked                                                                              
8              Slave Board FSU               Unchecked                                                                              
9              System Clock                  0.00                                                                                   
10             Peer System Clock             Unchecked                         
Table 3-207  Description of the display clock freq-deviation-detect-result command output

Item

Description

Reference

Sequence number of a clock source

Clock Source

Name of the clock source

Freq-Check-Result(Unit:ppm)

Check result of frequency offset

display clock hard-state

Function

The display clock hard-state command displays information about the hardware of the clock board, including the version and running status of the hardware.

Format

display clock hard-state [ slave ] [ chassis chassis-id ]

Parameters

Parameter

Description

Value

slave

Indicates the slave main control board.

-

chassis chassis-id

Specifies a chassis ID. This parameter is available only when the CSS function is enabled.

The value is 1 or 2.

Views

All views

Default Level

1: Monitoring level

Usage Guidelines

By using this command, you can check whether the board works normally.

Example

# Display information about the hardware of the clock board.

<HUAWEI> display clock hard-state
E1/T1 Framer Version   : 20                                                     
Clock Chip Version     : 21                                                     
FPGA Logic Version     : 201                                                    
FPGA Create Time       : 2009/09/21, 15:00                                      
1588 Logic Version     : 16                                                     
DSP CBB Version        : 2.01T00                                                
FPGA State             : Normal                                                 
E1/T1 Framer State     : Normal                                                 
DSP State              : Normal                                                 
Clock Chip State       : Normal                                                 
E1/T1 Framer OSC State : Normal                                                 
DSP OSC State          : Normal                                                 
Clock Chip OSC State   : Normal 
Table 3-208  Description of the display clock hard-state command output

Item

Description

E1/T1 Framer Version

Version of the E1/T1 framer.

Clock Chip Version

Version of the clock chip.

FPGA Logic Version

Logical version of the field programmable gate array (FPGA).

FPGA Create Time

Time when the FPGA is created.

1588 Logic Version

Logical version of the 1588 clock.

DSP CBB Version

Version of the digital signal processing common building block (DSP CBB).

FPGA State

State of the FPGA.

DSP State

State of the DSP.

E1/T1 Framer State

State of the E1/T1 framer.

E1/T1 Framer OSC State

Optical Supervisory Channel (OSC) state of the E1/T1 framer.

DSP OSC State

OSC state of the DSP.

Clock Chip State

State of the clock chip.

Clock Chip OSC State

OSC state of the clock chip.

display clock source-lost holdoff-time

Function

The display clock source-lost holdoff-time command displays the holdoff time for the system to consider a clock source lost.

Format

display clock source-lost holdoff-time [ chassis chassis-id ]

Parameters

Parameter

Description

Value

chassis chassis-id

Specifies a chassis ID. This parameter is available only when the CSS function is enabled.

The value is 1 or 2.

Views

All views

Default Level

1: Monitoring level

Usage Guidelines

After the holdoff time for the system to consider a clock source lost is set using the clock source-lost holdoff-time command, run the display clock source-lost holdoff-time command to view the configuration.

Example

# Set the holdoff time for the system to consider clock source 1 lost.

<HUAWEI> system-view
[HUAWEI] clock source-lost holdoff-time 3 source 1

# Display the holdoff time for the system to consider a clock source lost.

<HUAWEI> display clock source-lost holdoff-time
Reference      Clock Source                  Hold Off(unit:100ms)               
---------------------------------------------------------------------           
0              Inner Clock                   5                                  
1              BITS0                         3                                  
2              BITS1                         5                                  
3              Slave Board BITS0             5                                  
4              Slave Board BITS1             5                                  
5              Left Frame Clock              5                                  
6              Right Frame Clock             5                                  
Table 3-209  Description of the display clock source-lost holdoff-time command output

Item

Description

Reference

ID of the clock source

Clock Source

Name of the clock source

Hold Off (unit:100ms)

Holdoff time for the system to consider the clock source lost

display clock mode

Function

Using the display clock mode command, you can view the working mode of the clock source. By viewing the displayed information, you can check whether the SSM quality level is used in clock source selection, whether the check result of the clock frequency offset affects clock source selection, and whether the clock mode works in retrieve mode, and so on.

Format

display clock mode [ slave ] [ chassis chassis-id ]

Parameters

Parameter

Description

Value

slave

Indicates the slave main control board.

-

chassis chassis-id

Specifies a chassis ID. This parameter is available only when the CSS function is enabled.

The value is 1 or 2.

Views

All views

Default Level

1: Monitoring level

Usage Guidelines

This command displays the clock information, including whether the SSM quality level is used in clock source selection, whether the check result of the clock frequency offset affects clock source selection, clock holding mode, and status of the clock.

Example

# Display information about the clock module.

<HUAWEI> display clock mode
QL-Enable  : No.
Freq-Check : No.
Retrieve   : Yes.
Hold Type  : Hold 24 hours.
Run Mode   : Free.
Bits0      : Locked.
Bits1      : Locked.
System mode: Auto select clock source 0: Inner Clock.
Bits0 mode : Auto select clock source 9: System Clock.
Bits1 mode : Auto select clock source 9: System Clock.
Clock time : Free-run
Table 3-210  Description of the display clock mode command output

Item

Description

QL-Enable

Whether the SSM quality level is used in clock source selection.

Freq-Check

Whether the check result of the clock frequency offset affects clock source selection.

Retrieve

Whether a better clock source can replace the current clock source.

Hold Type

Whether the clock module works in permanent holding mode or 24-hour holding mode.

Run Mode

The clock chip can work in any of the following modes:
  • Tracing

    If a BITS clock or circuit clock is selected as the clock source, the clock chip needs to trace and lock the frequency of the clock. This task is performed by the PLL.

  • Holding

    When tracing an external clock (a BITS clock or circuit clock), the clock chip keeps saving the data of the clock.

    When the clock cannot be used as the clock source, the clock chip maintains the frequency of the clock source for a certain period (24 hours at most) according to the clock data saved previously.

    In permanent holding mode, the clock chip uses the last saved data as the output clock frequency.

  • Free running

    In free running mode, the clock chip uses the clock generated by the oscillator as the external clock.

Bits0

Whether the BITS0 clock is locked.

Bits1

Whether the BITS1 clock is locked.

System mode

Clock source selection mode of the system clock.

Bits0 mode

Clock source selection mode of the BITS0 clock.

Bits1 mode

Clock source selection mode of the BITS1 clock.

Clock time

Clock source of the clock board.

display clock { left-frame | right-frame }

Function

Using the display clock left-frame command, you can view information about an interface that sends the clock sources from the left side of the frame, including the priority of the clock source and whether the interface sends the clock source to the main control board.

Using the display clock right-frame command, you can view information about an interface that sends the clock sources from the right side of the frame, including the priority of the clock source and whether the interface sends the clock source to the main control board.

Format

display clock left-frame [ chassis chassis-id ]

display clock right-frame [ chassis chassis-id ]

Parameters

Parameter

Description

Value

chassis chassis-id

Specifies a chassis ID. This parameter is available only when the CSS function is enabled.

The value is 1 or 2.

Views

All views

Default Level

1: Monitoring level

Usage Guidelines

After running the clock priority priority-value command to set the priority of the clock source sent from an interface, you can run the display clock { left-frame | right-frame } command to check the configuration result.

Example

# Check the priority of the clock source that GigabitEthernet1/0/1 sends from the left side of the frame.

<HUAWEI> display clock left-frame
Interface                     Priority            Clock Signal Selected
---------------------------------------------------------------------
GigabitEthernet1/0/1          20                  N      
Table 3-211  Description of the display { clock left-frame | right-frame } command output

Item

Description

Interface

Interface number.

Priority

Priority of the clock source that the interface sends to the main control board.

Clock Signal Selected

Whether the interface sends the clock source to the main control board.

display clock lockout

Function

Using the display clock lockout command, you can check whether a clock source is locked, that is, whether it is excluded from clock source selection.

Format

display clock lockout [ chassis chassis-id ]

Parameters

Parameter

Description

Value

chassis chassis-id

Specifies a chassis ID. This parameter is available only when the CSS function is enabled.

The value is 1 or 2.

Views

All views

Default Level

1: Monitoring level

Usage Guidelines

After running the clock lockout command to exclude a clock source from clock source selection, you can run the display clock lockout command to check the configuration result.

Example

# Check whether clock source 5 is excluded from clock source selection.

<HUAWEI> display clock lockout
Reference Clock Source        System         Bits0          Bits1               
---------------------------------------------------------------------           
0         Inner Clock         No             -              -                   
1         BITS0               No             -              -                   
2         BITS1               No             -              -                   
3         Slave Board BITS0   No             -              -                   
4         Slave Board BITS1   No             -              -                   
5         Left Frame Clock    No             No             No                  
6         Right Frame Clock   No             No             No                  
7         FSU                 No             No             No                  
8         Slave Board FSU     No             No             No                  
9         System Clock        -              No             No                
Table 3-212  Description of the display clock lockout command output

Item

Description

Reference

Number of a clock source.

Clock Source

Name of a clock source.

System

System clock.

Bits0

BITS0 clock.

Bits1

BITS1 clock.

Related Topics

display clock priority

Function

Using the display clock priority command, you can view the priorities of clock sources.

Format

display clock priority [ chassis chassis-id ]

Parameters

Parameter

Description

Value

chassis chassis-id

Specifies a chassis ID. This parameter is available only when the CSS function is enabled.

The value is 1 or 2.

Views

All views

Default Level

1: Monitoring level

Usage Guidelines

After running the clock source priority command to set the priority of a clock source, you can run the display clock priority command to check the configuration result.

A smaller priority value indicates a higher priority.

Example

# Display priorities of clock sources.

<HUAWEI> display clock priority
Reference Clock Source        System         bits0          bits1               
---------------------------------------------------------------------           
0         Inner Clock         254            -              -                   
1         BITS0               1              -              -                   
2         BITS1               255            -              -                   
3         Slave Board BITS0   255            -              -                   
4         Slave Board BITS1   255            -              -                   
5         Left Frame Clock    255            255            255                 
6         Right Frame Clock   255            255            255                 
7         FSU                 255            255            255                 
8         Slave Board FSU     255            255            255                 
9         System Clock        -              254            254                 
Table 3-213  Description of the display clock priority command output

Item

Description

Reference

Number of a clock source.

Clock Source

Name of a clock source.

System

System clock.

bits0

BITS0 clock.

bits1

BITS1 clock.

display clock map unk

Function

The display clock map unk command displays the SSM quality level mapped to a clock source with the SSM quality level of UNK.

Format

display clock map unk

Parameters

None

Views

All views

Default Level

1: Monitoring level

Usage Guidelines

After an SSM quality level is mapped to a clock source with the SSM quality level of UNK using the clock map unk command, run the display clock map unk command to view the configuration.

Example

# Display the SSM quality level of a clock source with the SSM quality level of UNK.

<HUAWEI> system-view
[HUAWEI] display clock map unk
Info: The unknown quality level of the clock is SEC.
Table 3-214  Description of the display clock map unk command output

Item

Description

Clock unknown QL

Unknown SSM quality level

Related Topics

display clock selection

Function

Using the display clock selection command, you can view the result of clock source selection.

Format

display clock selection [ slave ] [ chassis chassis-id ]

Parameters

Parameter

Description

Value

slave

Indicates the slave main control board.

-

chassis chassis-id

Specifies a chassis ID. This parameter is available only when the CSS function is enabled.

The value is 1 or 2.

Views

All views

Default Level

1: Monitoring level

Usage Guidelines

This command displays the clock sources selected for the system clock, BITS0 clock, and BITS1 clock.

Example

# Display the result of clock source selection.

<HUAWEI> display clock selection
Type                          Clock Source Selected
-----------------------------------------------------------------
system                        5. Left Frame Clock
bits0                         5. Left Frame Clock
bits1                         9. System Clock
Table 3-215  Description of the display clock selection command output

Item

Description

Type

Type of a clock.

Clock Source Selected

Reference clock source selected for a clock.

display clock self-test-result

Function

Using the display clock self-test-result command, you can view the startup self-check information of the clock board.

Format

display clock self-test-result [ slave ] [ chassis chassis-id ]

Parameters

Parameter

Description

Value

slave

Indicates the slave main control board.

-

chassis chassis-id

Specifies a chassis ID. This parameter is available only when the CSS function is enabled.

The value is 1 or 2.

Views

All views

Default Level

1: Monitoring level

Usage Guidelines

By using this command, you can view the startup self-check information of the clock board to check whether the clock board works normally.

Example

# Display the startup self-check information of the clock board.

<HUAWEI> display clock self-test-result
FPGA State             : Normal
E1/T1 Framer State     : Normal
DSP State              : Normal
Clock Chip State       : Normal
E1/T1 Framer OSC State : Normal
DSP OSC State          : Normal
Clock Chip OSC State   : Normal   
Table 3-216  Description of the display clock self-test-result command output

Item

Description

FPGA state

Status of the field programmable gate array (FPGA).

E1/T1 Framer State

Status of the E1/T1 framer.

DSP state

Status of the DSP.

Clock Chip State

Status of the clock chip.

E1/T1 Framer OSC State

Status of the Optical Supervisory Channel (OSC) of the E1/T1 framer.

DSP OSC State

Status of the OSC of the DSP.

Clock Chip OSC State

Status of the OSC of the clock chip.

display clock source

Function

Using the display clock source command, you can view information about clock sources to check the SSM quality level of each clock source and whether the signal of any clock source is invalid, and so on.

Format

display clock source [ chassis chassis-id ]

Parameters

Parameter

Description

Value

chassis chassis-id

Specifies a chassis ID. This parameter is available only when the CSS function is enabled.

The value is 1 or 2.

Views

All views

Default Level

1: Monitoring level

Usage Guidelines

This command displays information about clock sources, including the S1 byte, clock id and SSM quality level of each clock source, and whether the signal of a clock source is invalid (signal-fail).

If the SSM quality level of a clock source can be obtained from the system automatically, the actual SSM quality level is displayed. If the SSM quality level of a clock source is set manually, for example, a BITS clock working in hz-2m mode, the manually set SSM quality level is displayed. If the SSM quality level of a clock source (except the inner clock and the system clock) cannot be obtained automatically or set manually, the SSM quality level is displayed as DNU. The SSM quality level of the inner clock and the system clock is displayed as SEC.

If you have run the clock id command to set the ID of a clock source, the display clock source command also displays the ID of the clock source. If the ID of a clock source is not set, the ID field in the output information is empty.

Example

# Display information about clock sources.

<HUAWEI> display clock source
Reference Clock Source        Signal Fail    S1 Byte     ID       SSM           
---------------------------------------------------------------------           
0         Inner Clock         No             --          -        SEC           
1         BITS0               Yes            --          1        DNU           
2         BITS1               Yes            --          -        DNU           
3         Slave Board BITS0   Yes            --          -        DNU           
4         Slave Board BITS1   Yes            --          -        DNU           
5         Left Frame Clock    Yes            --          -        DNU           
6         Right Frame Clock   Yes            --          -        DNU           
7         FSU                 Yes            --          -        DNU           
8         Slave Board FSU     Yes            --          -        DNU           
9         System Clock        No             --          -        SEC           
Table 3-217  Description of the display clock source command output

Item

Description

Reference

Number of a clock source.

Clock Source

Name of a clock source.

Signal Fail

Whether the signal of a clock source is invalid.

S1 Byte

S1 byte obtained from the circuit.

ID

ID of a clock source.

SSM

SSM quality level of a clock source.

display clock ssm-config

Function

Using the display clock ssm-config command, you can view the configured SSM quality levels of clock sources.

Format

display clock ssm-config [ chassis chassis-id ]

Parameters

Parameter

Description

Value

chassis chassis-id

Specifies a chassis ID. This parameter is available only when the CSS function is enabled.

The value is 1 or 2.

Views

All views

Default Level

1: Monitoring level

Usage Guidelines

After running the clock source source ssm { prc | ssua | ssub | sec | dnu } [ chassis chassis-id ] command to set the SSM quality level of a clock source, you can run the display clock ssm-config command to check the configuration result.

Example

# Display the SSM quality levels of clock sources.

<HUAWEI> display clock ssm-config
Reference      Clock Source                  SSM Config                         
---------------------------------------------------------------------           
0              Inner Clock                   ---                                
1              BITS0                         ---                                
2              BITS1                         ---                                
3              Slave Board BITS0             ---                                
4              Slave Board BITS1             ---                                
5              Left Frame Clock              ---                                
6              Right Frame Clock             ---                                
7              FSU                           ---                                
8              Slave Board FSU               ---                                
Table 3-218  Description of the display clock ssm-config command output

Item

Description

Reference

Number of a clock source.

Clock Source

Name of a clock source.

SSM Config

SSM quality level of a clock source.

display clock state

Function

Using the display clock state command, you can view the clock status on an interface.

Format

display clock state interface interface-type interface-number

Parameters

Parameter

Description

Value

interface interface-type interface-number

Specifies the type and number of an interface.

The interface number is selected according to the configuration of the device.

Views

All views

Default Level

1: Monitoring level

Usage Guidelines

Normally, the clock module sets the S1 byte to be sent according to the SSM level of the clock source.

Example

# Display the clock state on an interface where the priority of the clock source is not set.

<HUAWEI> display clock state interface gigabitethernet 1/0/0
Priority: 255.                                                                  
Send S1: 0F, Send SSM: DNU.                                                     
Force Out S1: No.                                                               
Id-out: Yes.     

# Display the clock state on an interface where the priority of the clock source is set.

<HUAWEI> display clock state interface gigabitethernet 1/0/0
SF(signal fail): No.
Priority: 0.
Recv S1: 0F, Recv SSM: DNU.
Send S1: 0F, Send SSM: DNU.
Force Out S1: No.
Id-out: Yes.
Table 3-219  Description of the display clock state command output

Item

Description

SF(signal fail)

Whether the clock source can provide valid clock signals.

Priority

The priority of the clock source.

Recv S1

S1 byte received by the interface.

Recv SSM

SSM quality level of the clock signal received by the interface.

Send S1

S1 byte sent by the interface.

Send SSM

SSM quality level of the clock signal sent by the interface.

Force Out s1

S1 byte that is sent forcibly. The lower four bits of the S1 byte indicate the SSM quality level, and the higher four bits of the S1 byte is the clock source ID used in extended mode.

Id-out

Whether the higher four bits of the S1 byte are used to transmit the clock source ID. If the value is no, it indicates that the higher four bits of the S1 byte are set to 0.

display clock wtr

Function

The display clock wtr command displays the WTR time of a clock source.

Format

display clock wtr [ chassis chassis-id ]

Parameters

Parameter

Description

Value

chassis chassis-id

Specifies a chassis ID. This parameter is available only when the CSS function is enabled.

The value is 1 or 2.

Views

All views

Default Level

1: Monitoring level

Usage Guidelines

After the WTR time of a clock source is set using the clock wtr wtr-time command, run the display clock wtr command to view the configuration.

Example

# Display the WTR time of a clock source

<HUAWEI> display clock wtr
Reference      Clock Source                  WTR(unit:minute)                   
---------------------------------------------------------------------           
0              Inner Clock                   1                                  
1              BITS0                         1                                  
2              BITS1                         1                                  
3              Slave Board BITS0             1                                  
4              Slave Board BITS1             1                                  
5              Left Frame Clock              1                                  
6              Right Frame Clock             1                                  
7              FSU                           1                                  
8              Slave Board FSU               1                                  
Table 3-220  Description of the display clock wtr command output

Item

Description

Reference

ID of the clock source

Clock Source

Name of the clock source

WTR(unit:minute)

WTR time of the clock source

Related Topics

snmp-agent trap enable feature-name clock

Function

The snmp-agent trap enable feature-name clock command enables the trap function of the clock module.

The undo snmp-agent trap enable feature-name clock command disables the trap function of the clock module.

By default, the trap function of the clock module is disabled.

Format

snmp-agent trap enable feature-name clock [ trap-name { hwclocksourcestatechange | hwclocksourceswitch | hwclocksourcesysclkworkmodechange } ]

undo snmp-agent trap enable feature-name clock [ trap-name { hwclocksourcestatechange | hwclocksourceswitch | hwclocksourcesysclkworkmodechange } ]

Parameters

Parameter Description Value
trap-name Enables the trap function of a specified event type. -
hwclocksourcestatechange Enables the trap function when the clock source state changes. -
hwclocksourceswitch Enables the trap function when a clock source switchover occurs. -
hwclocksourcesysclkworkmodechange Enables the trap function when the clock working mode changes. -

Views

System view

Default Level

2: Configuration level

Usage Guidelines

After the snmp-agent trap enable feature-name clock command is used, the trap function of the clock module is enabled.

To check whether "snmp-agent trap enable feature-name clock" exists, run the display current-configuration | include snmp command in all views. If the item exists, the trap function of the current clock module is enabled.

Example

# Enable the trap function of the clock module.

<HUAWEI> system-view
[HUAWEI] snmp-agent trap enable feature-name clock
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Updated: 2019-04-09

Document ID: EDOC1100065659

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