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Configuration Guide - Device Management

S7700 and S9700 V200R013C00

This document describes the configurations of Device Management, including device status query, hardware management, CSS, SVF, PoE, OPS, OIDS, energy-saving management, information center, fault management, NTP, synchronous ethernet, PTP.
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Example for Configuring the BITS as the Master Clock Source of PTP

Example for Configuring the BITS as the Master Clock Source of PTP

Networking Requirements

In Figure 14-17, the BITS clock connects to an external GPS clock, and the master clock connects to the BITS clock. Devices on the network cannot synchronize with the GPS clock. Therefore, GPS clock signals need to be obtained and transmitted on the network to allow the devices to synchronize with the GPS clock.

PTP can receive GPS clock signals from the BITS clock and transmit the clock signals on the network. This method ensures that devices on the network synchronize with the GPS clock.

Figure 14-17  Networking diagram of configuring the BITS as the master clock source of PTP

Configuration Roadmap

The configuration roadmap is as follows:

  1. Configure BITS interfaces (BITS0 and BITS1) of the master clock to connect to two clock sources. The BITS0 interface receives frequency signals, and the BITS1 interface receives time signals. Subsequently, GPS signals can be transmitted to the network through the BITS clock.

  2. Configure attributes for the BITS clock source to enable it to be selected as the best clock source.

  3. Configure the master clock as an OC to transmit clock signals to a downstream device.

Procedure

  1. Connect the BITS clock correctly. Ensure that the BITS0 interface receives frequency signals and the BITS1 interface receives time signals.
  2. Configure attributes for the input signals of the BITS clock. The default WTR time of a clock source is 1 minute, which does not need to be changed. To check the clock source switching result during commissioning, set the WTR time to 0 using the clock wtr command.

    <HUAWEI> system-view
    [HUAWEI] sysname Master
    [Master] clock bits-type hz-2m bits0
    [Master] clock source 1 priority 1 system
    [Master] clock manual source 1 system
    [Master] clock bits-type 1pps-tod in bits1
    [Master] ptp clock-source bits1 on
    

  3. Configure attributes for the BITS clock source on the master clock. BITS1 connects to an external time source GPS, so its time-source is 2.

    [Master] ptp clock-source bits1 time-source 2

  4. Enable PTP on the master clock and configure the device type as OC.

    [Master] ptp enable
    [Master] ptp device-type oc
    [Master] interface gigabitethernet 1/0/0
    [Master-GigabitEthernet1/0/0] ptp delay-mechanism pdelay
    [Master-GigabitEthernet1/0/0] ptp enable
    [Master-GigabitEthernet1/0/0] quit
    [Master] quit

  5. Verify the configuration.

    # Run the display clock source command on the master clock. The command output shows that the Signal Fail field displays No for the BITS0 and BITS1 interfaces of the master clock. This indicates that the master clock has traced the BITS clock source.

    <Master> display clock source
    Reference Clock Source        Signal Fail    S1 Byte     ID       SSM
    ---------------------------------------------------------------------
    0         Inner Clock         No             --          -        SEC
    1         BITS0               No             0f          -        DNU
    2         BITS1               No             0f          -        DNU
    3         Peer Board BITS0    Yes            --          -        DNU
    4         Peer Board BITS1    Yes            --          -        DNU
    5         Left Frame Clock    Yes            --          -        DNU
    6         Right Frame Clock   Yes            --          -        DNU
    7         FSU                 Yes            --          -        DNU
    8         Peer Board FSU      Yes            --          -        DNU
    9         System Clock        No             --          -        DNU
    

    # Run the display clock mode command on the master clock. The command output shows that the master clock is locked and tracing the frequency signals of the BITS0 interface.

    <Master> display clock mode
    QL-Enable  : No.
    Freq-Check : No.
    Retrieve   : Yes.
    Hold Type  : Hold 24 hours.
    Run Mode   : Trace.(SyncOK)
    Bits0      : Locked.
    Bits1      : Locked.
    System mode: Manual-switch to clock source 1: BITS0.
    Bits0 mode : Auto select clock source 9: System Clock.
    Bits1 mode : Auto select clock source 9: System Clock.
    Clock time : 1pps-tod time from bits1

    # Run the display ptp all command on the master clock. The command output shows the current PTP running status of the master clock.

    <Master> display ptp all
    Device config info
      ------------------------------------------------------------------
      PTP state         :enabled    Domain  value      :0
      Slave only        :no         Device type        :OC
      Static BMC        :no         Local clock ID     :00e0fcfffe010203
      PTP freq-sync     :no         Time lock success  :yes                         
      PTP acl           :no                                                         
    
      BMC run info
      ------------------------------------------------------------------
      Source port       :bits1
      Leap              :None
      UTC Offset        :0
      UTC Offset Valid  :False
    
      Port info
      Name                   State        Delay-mech Ann-timeout Type Domain         
      ------------------------------------------------------------------------
      GigabitEthernet1/0/0   master       pdelay     9           OC   0 
    
      Clock source info
      Clock Pri1 Pri2 Accuracy Class TimeSrc Signal Switch Direction In-Status
      ------------------------------------------------------------------------
      local 128  128  0x31     187   0xa0     -      -      -         -
      bits0 128  128  0x20       6   0x20     none   off   -/-        abnormal
      bits1   0  128  0x10       1   0x20     1pps   on    in/-       normal

Configuration File

  • Master clock configuration file

    #
    sysname Master
    #
    clock source 1 priority 1 system
    clock bits-type hz-2m bits0
    clock bits-type 1pps-tod in bits1
    #
    ptp enable
    ptp device-type oc
    ptp clock-source bits1 on
    #
    interface GigabitEthernet1/0/0 
     ptp delay-mechanism pdelay                                                     
     ptp enable
    #
    return
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Updated: 2019-04-20

Document ID: EDOC1100065738

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