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Configuration Guide - Device Management

S7700 and S9700 V200R013C00

This document describes the configurations of Device Management, including device status query, hardware management, CSS, SVF, PoE, OPS, OIDS, energy-saving management, information center, fault management, NTP, synchronous ethernet, PTP.
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Example for Selecting the Clock Source Based on the Priority

Example for Selecting the Clock Source Based on the Priority

Networking Requirements

On a ring network, the clock of a switch is configured as the primary reference clock. You can set the priorities of clock sources so that these priorities are used to determine clock source selection. In addition, you must prevent timing loops from occurring. A timing loop occurs if the device where the primary reference clock is located receives clock signals from a clock source with higher priority and the clock source of the primary reference clock is re-selected.

As shown in Figure 13-17, three switches form a ring network. The clock of SwitchA is the primary reference clock. The switches obtain clock signals from the LPUs and select clock sources based on priorities. The red arrows indicate the clock synchronization direction during normal operation. If the clock signal fails to be transmitted in this direction, the switches can quickly change the clock synchronization direction, as shown by the blue arrows. SwitchA is always the reference clock source.

Figure 13-17  Networking diagram for selecting the clock source based on the priority

Configuration Roadmap

The configuration roadmap is as follows:
  1. Configure the routing protocol to make the IP routes between the nodes reachable.
  2. Configure the BITS0 interface of SwitchA to use the BITS clock as the input primary reference clock.
  3. Set the mode of clock source selection on SwitchB and SwitchC. Ensure that the priority of the clock signals sent from the left side of the frame is higher than that of the clock signals sent from the right side of the frame on each switch. Clock source selection proceeds in the direction shown by the red arrows.

Procedure

  1. Verify that the clock of SwitchA is the primary reference clock.

    # Set the priority of the BITS0 clock on SwitchA to 1.

    <HUAWEI> system-view
    [HUAWEI] sysname SwitchA
    [SwitchA] clock source 1 priority 1 system 
    

    # Configure the SSM quality levels not to be used in clock source selection.

    [SwitchA] clock ssm-control off
    

    # Verify that the system clock selects the BITS0 clock as the clock source and that the system clock sends the clock signal to the LPUs as the output clock signal.

    [SwitchA] display clock selection
    Type                         Clock Source Selected
    ---------------------------------------------------------------------
    system                        1.    BITS0
    bits0                         9.    System Clock
    bits1                         9.    System Clock
    

  2. Set the mode of clock source selection on SwitchB.

    # On SwitchB, set the priority to 10 for the clock signals that GigabitEthernet 5/0/7 in the right side of the frame sends to the clock board, and set the priority to 20 for the clock signals that GigabitEthernet 5/0/3 in the right side of the frame sends to the clock board. Retain the default WTR time. Set the priority to 6 for the clock signals sent from the right side of the frame.
    NOTE:

    To view the clock source switching result during debugging, set the WTR time to 0.

    <HUAWEI> system-view
    [HUAWEI] sysname SwitchB
    [SwitchB] interface gigabitethernet 5/0/7
    [SwitchB-GigabitEthernet5/0/7] clock priority 10
    [SwitchB-GigabitEthernet5/0/7] quit
    [SwitchB] interface gigabitethernet 5/0/3
    [SwitchB-GigabitEthernet5/0/3] clock priority 20
    [SwitchB-GigabitEthernet5/0/3] quit
    [SwitchB] clock source 6 priority 6 system
    
    # View information about the clock sources sent from the right side of the frame. The following output indicates that the clock source of GigabitEthernet 5/0/7 is sent to the clock board. The clock synchronization direction is shown by the red arrows in Figure 13-17.
    [SwitchB] display clock right-frame
    Interface                     Priority            Clock Signal Selected
    ---------------------------------------------------------------------
    GigabitEthernet5/0/3          20                  N
    GigabitEthernet5/0/7          10                  Y
    

    # View the clock information on SwitchB. The following output indicates that the inner clock, Right Frame Clock, and system clock provide clock signals normally.

    [SwitchB] display clock source
    Reference Clock Source        Signal Fail    S1 Byte     ID       SSM
    ---------------------------------------------------------------------
    0         Inner Clock         No             --          -        SEC
    1         BITS0               Yes            --          -        DNU           
    2         BITS1               Yes            --          -        DNU           
    3         Slave Board BITS0   Yes            --          -        DNU           
    4         Slave Board BITS1   Yes            --          -        DNU           
    5         Left Frame Clock    Yes            --          -        DNU           
    6         Right Frame Clock   No             0f          -        DNU
    7         FSU                 Yes            --          -        DNU           
    8         Slave Board FSU     Yes            --          -        DNU           
    9         System Clock        No             --          -        SEC           
    

    # Configure the SSM quality levels not to be used in clock source selection.

    [SwitchB] clock ssm-control off
    

    # Verify that the system clock selects the clock source sent from the right side of the frame as the clock source and that the system clock sends the clock signal to the LPUs as the output clock signal.

    [SwitchB] display clock selection
    Type                         Clock Source Selected
    ---------------------------------------------------------------------
    system                        6.    Right Frame Clock
    bits0                         9.    System Clock
    bits1                         9.    System Clock
    

  3. Set the mode of clock source selection on SwitchC.

    # On SwitchC, set the priority to 30 for the clock signal that GigabitEthernet 2/0/3 sends from the left side of the frame to the clock board, and set the priority to 40 for the clock signal that GigabitEthernet 2/0/0 sends from the left side of the frame to the clock board. Retain the default WTR time. Set the priority to 5 for the clock signals sent from the left side of the frame.
    NOTE:

    To view the clock source switching result during debugging, set the WRT time to 0.

    <HUAWEI> system-view
    [HUAWEI] sysname SwitchC
    [SwitchC] interface gigabitethernet 2/0/3
    [SwitchC-GigabitEthernet2/0/3] clock priority 30
    [SwitchC-GigabitEthernet2/0/3] quit
    [SwitchC] interface gigabitethernet 2/0/0
    [SwitchC-GigabitEthernet2/0/0] clock priority 40
    [SwitchC-GigabitEthernet2/0/0] quit
    [SwitchC] clock source 5 priority 5 system
    
    # View information about the clock sources sent from the left side of the frame. The following output indicates that the clock source of GigabitEthernet2/0/3 is sent to the clock board. The clock synchronization direction is shown by the red arrows in Figure 13-17.
    [SwitchC] display clock left-frame
    Interface                     Priority            Clock Signal Selected
    ---------------------------------------------------------------------
    GigabitEthernet2/0/0          40                  N
    GigabitEthernet2/0/3          30                  Y
    

    # View the clock information on SwitchC. The following output indicates that the inner clock, Left Frame Clock, and system clock provide clock signals normally.

    [SwitchC] display clock source
    Reference Clock Source        Signal Fail    S1 Byte     ID       SSM
    ---------------------------------------------------------------------
    0         Inner Clock         No             --          -        SEC
    1         BITS0               Yes            --          -        DNU           
    2         BITS1               Yes            --          -        DNU           
    3         Slave Board BITS0   Yes            --          -        DNU           
    4         Slave Board BITS1   Yes            --          -        DNU           
    5         Left Frame Clock    No             0f          -        DNU
    6         Right Frame Clock   Yes            --          -        DNU
    7         FSU                 Yes            --          -        DNU           
    8         Slave Board FSU     Yes            --          -        DNU           
    9         System Clock        No             --          -        SEC           
    

    # Configure the SSM quality levels not to be used in clock source selection.

    [SwitchC] clock ssm-control off
    

    # Verify that the system clock selects the clock source sent from the left side of the frame as the clock source and that the system clock sends the clock signal to the LPUs as the output clock signal.

    [SwitchC] display clock selection
    Type                         Clock Source Selected
    ---------------------------------------------------------------------
    system                        5.    Left Frame Clock
    bits0                         9.    System Clock
    bits1                         9.    System Clock
    

  4. Verify the configuration.

    The commands used to verify the configuration result are included in the preceding steps.

Configuration Files

  • SwitchA configuration file

    #
    sysname SwitchA
    #
    clock source 1 priority 1 system
    #
    return
  • SwitchB configuration file

    #
     sysname SwitchB
    #
    clock source 6 priority 6 system
    #
    interface GigabitEthernet5/0/3
     clock priority 20
    #
    interface GigabitEthernet5/0/7
     clock priority 10
    #
    return
  • SwitchC configuration file

    #
     sysname SwitchC
    #
    clock source 5 priority 5 system
    #
    interface GigabitEthernet2/0/0
     clock priority 40
    #
    interface GigabitEthernet2/0/3
     clock priority 30
    #
    return
Translation
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Updated: 2019-04-20

Document ID: EDOC1100065738

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