Configuration Guide - Device Management

Timing Loop Prevention

A timing loop occurs when a clock traces its own clock signals. The following methods can be used to prevent timing loops.

• Set the SSM quality level of a line clock used as a clock source to DNU. This prevents timing loops that may occur on the peer device because a clock source whose SSM quality level is set as DNU does not participate in clock source selection. Figure 13-10 shows the implementation.

  Figure 13-10  Timing loop prevention
  
  

• Use the extended clock source selection mode with the SSM quality level.

  This mode is developed by Huawei and has been used as a standard in China. Implementation of this mode is as follows:

  • On synchronous Ethernet networks, an SSM quality level occupies the left-most four bits of the S1 byte and the clock source ID occupies the right-most four bits.

  • On a simple ring network, if a path becomes Down, clock signals are transmitted over the reverse path. The original clock source can be identified using a clock source ID, thereby preventing timing loops.

    On a complex network, clock source IDs may not eliminate all timing loops because only 16 clock source IDs are available. In addition, on a subnet that does not contain the original clock source, timing loops cannot be prevented. To address this issue, subnetting can be used.

  • A complex network can be divided into two or more subnets. On a subnet, clock source IDs are allocated by the network designer. The following figure is an example of subnetting.

    Figure 13-11  Subnetting
    
    

    In Figure 13-11, two rings are connected over two paths. The network contains only two available reference clock sources. If IDs are set for the two sources and the paths between the two rings fail, the ID of the original reference clock source for the right ring cannot be terminated. This is because the ID originates from the left ring. In this case, a timing loop occurs.

    To address this issue, divide the network into two subnets, namely, left ring and right ring.

    • Specify the master and slave BITS sources on the left ring.

    • Specify the two links as the master and slave reference clock sources for the right ring.

    By setting clock source IDs, you can logically separate the left and right rings. On network element C on the right ring, set an ID for link a. Similarly, set an ID for link b on network element D. If faults occur on link a and link b, no timing loop occurs because the right ring has a defined clock source ID.

    NOTE:

    The clock source ID set on the right ring identifies the reference clock source and separates the right ring from the left ring. The clock source ID set on the left ring cannot be sent to the right ring through link a or link b, and the right ring can receive only the SSM quality level from the left ring. The clock source IDs configured on the right ring can be the same as those configured on the left ring, eliminating the 16 ID limit.