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Configuration Guide - Device Management

S7700 and S9700 V200R013C00

This document describes the configurations of Device Management, including device status query, hardware management, CSS, SVF, PoE, OPS, OIDS, energy-saving management, information center, fault management, NTP, synchronous ethernet, PTP.
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Example for Selecting the Clock Source Based on the SSM Quality Level

Example for Selecting the Clock Source Based on the SSM Quality Level

Networking Requirements

On a ring network, the clock of a switch is configured as the primary reference clock. You can set the priorities of clock sources so that the clock source is selected based on the SSM quality level. In addition, you must prevent timing loops from occurring.

As shown in Figure 13-18, three switches form a ring network. The clock of SwitchA is the primary reference clock. The switches obtain clock signals from the LPUs and select the clock source based on the SSM quality level. The red arrows indicate the clock synchronization direction during normal operation. If the clock signal fails to be transmitted in this direction, the switches can quickly change the clock synchronization direction, as shown by the blue arrows.

Figure 13-18  Networking diagram for selecting the clock source based on the SSM quality level

Configuration Roadmap

The configuration roadmap is as follows:
  1. Configure the routing protocol to make the IP routes between the nodes reachable.
  2. Configure the BITS0 interface of SwitchA to use the BITS clock as the input primary reference clock. (The SSM quality level of the BITS0 clock is PRC.)
  3. Set the mode of clock source selection on SwitchA, SwitchB and SwitchC.

Procedure

  1. Verify that the clock of SwitchA is the primary reference clock and enable the SSM quality level to be used in clock source selection.

    # On SwitchA, enable the SSM quality level to be used in clock source selection and set the priority of the BITS0 clock to 1.

    <HUAWEI> system-view
    [HUAWEI] sysname SwitchA
    [SwitchA] clock ssm-control on
    [SwitchA] clock source 1 priority 1 system

    # View the clock information on SwitchA. The following output indicates that the inner clock and system clock provide clock signals normally.

    [SwitchA] display clock source
    Reference Clock Source        Signal Fail    S1 Byte     ID       SSM
    ---------------------------------------------------------------------
    0         Inner Clock         No             --          -        SEC
    1         BITS0               No             --          -        PRC
    2         BITS1               Yes            --          -        DNU
    3         Slave Board BITS0   Yes            --          -        DNU
    4         Slave Board BITS1   Yes            --          -        DNU
    5         Left Frame Clock    Yes            --          -        DNU
    6         Right Frame Clock   Yes            --          -        DNU
    7         System Clock        No             --          -        PRC
    

    # Verify that the SSM quality level is used in clock source selection.

    [SwitchA] display clock mode
    QL-Enable  : Yes.
    Freq-Check : No.
    Retrieve   : Yes.
    Hold Type  : Hold 24 hours.
    Run Mode   : Free.
    Bits0      : Locked.
    Bits1      : Locked.
    System mode: Auto select clock source 1: BITS0.
    Bits0 mode : Auto select clock source 9: System Clock.
    Bits1 mode : Auto select clock source 9: System Clock.
    Clock time : Free-run
    

    # Verify that the system clock selects the BITS0 clock as the clock source and that the system clock sends the clock signal to the LPUs as the output clock signal.

    [SwitchA] display clock selection
    Type                         Clock Source Selected
    ---------------------------------------------------------------------
    system                        1.    BITS0
    bits0                         9.    System Clock
    bits1                         9.    System Clock
    

  2. Set the mode of clock source selection on SwitchB.

    # On SwitchB, set the priority to 10 for the clock signal that GigabitEthernet5/0/7 sends from the right side of the frame, and set priority to 20 for the clock signal that GigabitEthernet5/0/3 sends from the right side of the frame. Retain the default WTR time. Set the priority to 6 for the clock signal sent from the right side of the frame.
    NOTE:

    To view the clock source switching result during debugging, set the WTR time to 0.

    <HUAWEI> system-view
    [HUAWEI] sysname SwitchB
    [SwitchB] clock ssm-control on
    [SwitchB] interface gigabitethernet 5/0/7
    [SwitchB-GigabitEthernet5/0/7] clock priority 10
    [SwitchB-GigabitEthernet5/0/7] quit
    [SwitchB] interface gigabitethernet 5/0/3
    [SwitchB-GigabitEthernet5/0/3] clock priority 20
    [SwitchB-GigabitEthernet5/0/3] quit
    [SwitchB] clock source 6 priority 6 system
    
    # View information about the clock sources sent from the right side of the frame. The following output indicates the clock source of GigabitEthernet 5/0/7 is sent to the clock board. The clock synchronization direction is shown by the red arrows in Figure 13-18.
    [SwitchB] display clock right-frame
    Interface                     Priority            Clock Signal Selected
    ---------------------------------------------------------------------
    GigabitEthernet5/0/3          20                  N
    GigabitEthernet5/0/7          10                  Y
    

    # View the clock information on SwitchB. The following output indicates that the inner clock, Right Frame Clock, and system clock provide clock signals normally.

    [SwitchB] display clock source
    Reference Clock Source        Signal Fail    S1 Byte     ID       SSM           
    ---------------------------------------------------------------------           
    0         Inner Clock         No             --          -        SEC           
    1         BITS0               Yes            --          -        DNU           
    2         BITS1               Yes            --          -        DNU           
    3         Slave Board BITS0   Yes            --          -        DNU           
    4         Slave Board BITS1   Yes            --          -        DNU           
    5         Left Frame Clock    No             --          -        PRC           
    6         Right Frame Clock   Yes            --          -        DNU           
    7         FSU                 Yes            --          -        DNU           
    8         Slave Board FSU     Yes            --          -        DNU           
    9         System Clock        No             --          -        PRC          

    # Verify that the SSM quality level is used in clock source selection.

    [SwitchB] display clock mode
    QL-Enable  : Yes.
    Freq-Check : No.
    Retrieve   : Yes.
    Hold Type  : Hold 24 hours.
    Run Mode   : Trace.(SyncOK, Locked)
    Bits0      : Locked.
    Bits1      : Locked.
    System mode: Auto select clock source 6: Right Frame Clock.
    Bits0 mode : Auto select clock source 9: System Clock.
    Bits1 mode : Auto select clock source 9: System Clock.
    Clock time : Free-run
    

    # Ensure that the system clock selects the clock source sent from the right side of the frame as the clock source and that the system clock sends clock signal to the LPUs as the output clock signal.

    [SwitchB] display clock selection
    Type                         Clock Source Selected
    ---------------------------------------------------------------------
    system                        6.    Right Frame Clock
    bits0                         9.    System Clock
    bits1                         9.    System Clock
    

  3. Set the mode of clock source selection on SwitchC.

    # On SwitchC, set the priority to 30 for the clock signal that GigabitEthernet2/0/3 sends from the left side of the frame, and set priority to 40 for the clock signal that GigabitEthernet2/0/0 sends from the left side of the frame. Retain the default WTR time. Set the priority to 5 for the clock signal sent from the left side of the frame.
    NOTE:

    To view the clock source switching result during debugging, set the WTR time to 0.

    <HUAWEI> system-view
    [HUAWEI] sysname SwitchC
    [SwitchC] clock ssm-control on
    [SwitchC] interface gigabitethernet 2/0/3
    [SwitchC-GigabitEthernet2/0/3] clock priority 30
    [SwitchC-GigabitEthernet2/0/3] quit
    [SwitchC] interface gigabitethernet 2/0/0
    [SwitchC-GigabitEthernet2/0/0] clock priority 40
    [SwitchC-GigabitEthernet2/0/0] quit
    [SwitchC] clock source 5 priority 5 system
    
    # View information about the clock sources sent from the left side of the frame. The following output indicates the clock source of GigabitEthernet 2/0/3 is sent to the clock board. The clock synchronization direction is shown by the red arrows in Figure 13-18.
    [SwitchC] display clock left-frame
    Interface                     Priority            Clock Signal Selected
    ---------------------------------------------------------------------
    GigabitEthernet2/0/0          40                  N
    GigabitEthernet2/0/3          30                  Y
    

    # View the clock information on SwitchC. The following output indicates that the inner clock, Left Frame Clock, and system clock provide clock signals normally.

    [SwitchC] display clock source
    Reference Clock Source        Signal Fail    S1 Byte     ID       SSM           
    ---------------------------------------------------------------------           
    0         Inner Clock         No             --          -        SEC           
    1         BITS0               Yes            --          -        DNU           
    2         BITS1               Yes            --          -        DNU           
    3         Slave Board BITS0   Yes            --          -        DNU           
    4         Slave Board BITS1   Yes            --          -        DNU           
    5         Left Frame Clock    No             --          -        PRC           
    6         Right Frame Clock   Yes            --          -        DNU           
    7         FSU                 Yes            --          -        DNU           
    8         Slave Board FSU     Yes            --          -        DNU           
    9         System Clock        No             --          -        PRC          

    # Verify that the SSM quality level is used in clock source selection.

    [SwitchC] display clock mode
    QL-Enable  : Yes.
    Freq-Check : No.
    Retrieve   : Yes.
    Hold Type  : Hold 24 hours.
    Run Mode   : Trace.(SyncOK, Locked)
    Bits0      : Locked.
    Bits1      : Locked.
    System mode: Auto select clock source 5: Left Frame Clock.
    Bits0 mode : Auto select clock source 9: System Clock.
    Bits1 mode : Auto select clock source 9: System Clock.
    Clock time : Free-run
    

    # Ensure that the system clock selects the clock source sent from the left side of the frame as the clock source and that the system clock sends clock signal to the LPUs as the output clock signal.

    [SwitchC] display clock selection
    Type                         Clock Source Selected
    ---------------------------------------------------------------------
    system                        5.    Left Frame Clock
    bits0                         9.    System Clock
    bits1                         9.    System Clock
    

  4. Verify the configuration.

    The commands used to verify the configuration result are included in the preceding steps.

Configuration Files

  • SwitchA configuration file

    #
    sysname SwitchA
    #
    clock ssm-control on
    clock source 1 priority 1 system
    #
    return
  • SwitchB configuration file

    #
    sysname SwitchB
    #
    clock ssm-control on
    clock source 6 priority 6 system
    #
    interface GigabitEthernet5/0/3
     clock priority 20
    #
    interface GigabitEthernet5/0/7
     clock priority 10
    #
    return
  • SwitchC configuration file

    #
     sysname SwitchC
    #
    clock ssm-control on
    clock source 5 priority 5 system
    #
    interface GigabitEthernet2/0/0
     clock priority 40
    #
    interface GigabitEthernet2/0/3
     clock priority 30
    #
    return
Translation
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Updated: 2019-04-20

Document ID: EDOC1100065738

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