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Configuration Guide - Device Management

CloudEngine 12800 and 12800E V200R005C10

This document describes the configurations of Device Management, including device status query, hardware management, Information Center Configuration, NTP, Synchronous Ethernet Configuration, Fault Management Configuration, Energy-Saving Management Configuration, Performance Management Configuration, Maintenance Assistant Configuration, and OPS Configuration.
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Example for Configuring Clock Synchronization on a Hybrid Network

Example for Configuring Clock Synchronization on a Hybrid Network

Networking Requirements

Figure 5-16 shows a hybrid clock synchronization network consisting of a ring network and a chain network. Device1, Device2, and Device3 reside on the same ring clock synchronization network. Device1 is connected to an external clock, and Device3 is directly connected to Device4 on the chain clock synchronization network. Device4 is a stack of two switches.

On the hybrid clock synchronization network, when the external clock is working normally, each device traces high-quality clock signals of the external clock. When the external clock is faulty, all devices trace clock signals of Device4 on the chain clock synchronization network.

Figure 5-16 Configuring clock synchronization on a hybrid network

Table 5-3 Clock source priority of each device

Device

Clock Source in Use

Priority

Device1

10GE1/0/1

-

10GE1/0/2

3

BITS0

1

Device2

10GE1/0/1

1

10GE1/0/2

2

Device3

10GE1/0/1

2

10GE1/0/2

-

10GE1/0/3

3

Device4

10GE1/1/0/4

1

Configuration Roadmap

The configuration roadmap is as follows:

  1. Configure the clock source type.
  2. Configure the clock source priority.

Procedure

  1. Configure Device4 as a stack. For details, see Example for Configuring a Stack (in MPU Connection Mode). In the stack, stack member ports are 10GE1/1/0/1, 10GE1/1/0/2, 10GE2/1/0/1, and 10GE2/1/0/2.
  2. Configure Device1.

    <HUAWEI> system-view
    [~HUAWEI] sysname Device1
    [*HUAWEI] commit
    [~Device1] clock bits-type bits0 2mbps
    [*Device1] clock source bits0 synchronization enable
    [*Device1] clock source bits0 priority 1
    [*Device1] commit
    [~Device1] interface 10ge 1/0/1
    [~Device1-10GE1/0/1] clock synchronization enable
    [*Device1-10GE1/0/1] commit
    [~Device1-10GE1/0/1] quit
    [~Device1] interface 10ge 1/0/2
    [~Device1-10GE1/0/2] clock synchronization enable
    [*Device1-10GE1/0/2] clock priority 3
    [*Device1-10GE1/0/2] commit
    [~Device1-10GE1/0/2] quit

  3. Configure Device2.

    <HUAWEI> system-view
    [~HUAWEI] sysname Device2
    [*HUAWEI] commit
    [~Device2] interface 10ge 1/0/1
    [~Device2-10GE1/0/1] clock synchronization enable
    [*Device2-10GE1/0/1] clock priority 1
    [*Device2-10GE1/0/1] commit
    [~Device2-10GE1/0/1] quit
    [~Device2] interface 10ge 1/0/2
    [~Device2-10GE1/0/2] clock synchronization enable
    [*Device2-10GE1/0/2] clock priority 2
    [*Device2-10GE1/0/2] commit
    [~Device2-10GE1/0/2] quit

  4. Configure Device3.

    <HUAWEI> system-view
    [~HUAWEI] sysname Device3
    [*HUAWEI] commit
    [~Device3] interface 10ge 1/0/1
    [~Device3-10GE1/0/1] clock synchronization enable
    [*Device3-10GE1/0/1] clock priority 2
    [*Device3-10GE1/0/1] commit
    [~Device3-10GE1/0/1] quit
    [~Device3] interface 10ge 1/0/2
    [~Device3-10GE1/0/2] clock synchronization enable
    [*Device3-10GE1/0/2] commit
    [~Device3-10GE1/0/2] quit
    [~Device3] interface 10ge 1/0/3
    [~Device3-10GE1/0/3] clock synchronization enable
    [*Device3-10GE1/0/3] clock priority 3
    [*Device3-10GE1/0/3] commit
    [~Device3-10GE1/0/3] quit

  5. Configure Device4.

    # In the stack, set the clock link mode of stack member ports to the interlink mode.
    <HUAWEI> system-view
    [~HUAWEI] sysname Device4
    [*HUAWEI] commit
    [~Device4] interface 10ge 1/1/0/1
    [~Device4-10GE1/1/0/1] clock link-mode interlink
    [*Device4-10GE1/1/0/1] commit
    [~Device4-10GE1/1/0/1] quit
    [~Device4] interface 10ge 1/1/0/2
    [~Device4-10GE1/1/0/2] clock link-mode interlink
    [*Device4-10GE1/1/0/2] commit
    [~Device4-10GE1/1/0/2] quit
    [~Device4] interface 10ge 2/1/0/1
    [~Device4-10GE2/1/0/1] clock link-mode interlink
    [*Device4-10GE2/1/0/1] commit
    [~Device4-10GE2/1/0/1] quit
    [~Device4] interface 10ge 2/1/0/2
    [~Device4-10GE2/1/0/2] clock link-mode interlink
    [*Device4-10GE2/1/0/2] commit
    [~Device4-10GE2/1/0/2] quit
    # Configure the clock source priority.
    [~Device4] interface 10ge 1/1/0/4
    [~Device4-10GE1/1/0/4] clock synchronization enable
    [*Device4-10GE1/1/0/4] clock priority 1
    [*Device4-10GE1/1/0/4] commit
    [~Device4-10GE1/1/0/4] quit

  6. Verify the configuration.

    # Run the display clock source command on Device4 to check the clock source traced by the system clock and status of each clock source.

    [~Device4] display clock source
      System trace source State:   lock mode                                        
                                   into pull-in range                               
      Current system trace source: 10GE1/1/0/4                                       
      Frequency lock success:      yes                                               
                                                                                    
      Master board                                                                  
      Source        Pri(sys)   In-SSM   Out-SSM   State          Ref-Source         
      ------------------------------------------------------------------------------
      10GE1/1/0/4    1          dnu      dnu       normal         yes                

    # Run the display clock cluster frequency source command on Device4 to check the frequency synchronization status of the stack.

    [~Device4] display clock cluster frequency source
    Chassis                                                                         
      Chassis   Trace-state   Pull-in   Trace-source                  Lock           
    --------------------------------------------------------------------------      
      1         lock          into      --                             yes            
      2         lock          into      10GE2/1/0/1                    yes            
                                                                                    
    Port                                                                            
      Source                        Peer Port                      State              
    ----------------------------------------------------------------------          
      10GE1/1/0/1                   10GE2/1/0/1                    normal              
      10GE1/1/0/2                   10GE2/1/0/2                    normal              
      10GE2/1/0/1                   10GE1/1/0/1                    normal              
      10GE2/1/0/2                   10GE1/1/0/2                    normal              

Configuration Files

  • Device1 configuration file

    #
    sysname Device1
    #
    clock source bits0 synchronization enable slot 5
    clock source bits0 priority 1 slot 5
    clock bits-type bits0 2mbps slot 5
    #
    interface 10GE1/0/1
     clock synchronization enable
    #
    interface 10GE1/0/2
     clock synchronization enable
     clock priority 3
    #
    return
  • Device2 configuration file

    #
    sysname Device2
    #
    interface 10GE1/0/1
     clock synchronization enable
     clock priority 1
    #
    interface 10GE1/0/2
     clock synchronization enable
     clock priority 2
    #
    return
  • Device3 configuration file

    #
    sysname Device3
    #
    interface 10GE1/0/1
     clock synchronization enable
     clock priority 2
    #
    interface 10GE1/0/2
     clock synchronization enable
    #
    interface 10GE1/0/3
     clock synchronization enable
     clock priority 3
    #
    return
  • Device4 configuration file

    #
    sysname Device4
    #
    interface Stack-Port1/1
    #
    interface Stack-Port2/1
    #
    interface 10GE1/1/0/1
     port mode stack
     stack-port 1/1
     clock link-mode interlink
    #
    interface 10GE1/1/0/2
     port mode stack
     stack-port 1/1
     clock link-mode interlink
    #
    interface 10GE1/1/0/4
     clock synchronization enable
     clock priority 1
    #
    interface 10GE2/1/0/1
     port mode stack
     stack-port 2/1
     clock link-mode interlink
    #
    interface 10GE2/1/0/2
     port mode stack
     stack-port 2/1
     clock link-mode interlink
    #
    return
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Updated: 2019-04-20

Document ID: EDOC1100074722

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