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Configuration Guide - Device Management

CloudEngine 12800 and 12800E V200R005C10

This document describes the configurations of Device Management, including device status query, hardware management, Information Center Configuration, NTP, Synchronous Ethernet Configuration, Fault Management Configuration, Energy-Saving Management Configuration, Performance Management Configuration, Maintenance Assistant Configuration, and OPS Configuration.
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Example for Configuring Time synchronization (Static 1588v2)

Example for Configuring Time synchronization (Static 1588v2)

Networking Requirements

In Figure 6-22, these devices reside on a Layer 2 network, and PE1 and PE2 each are connected to an external clock. All devices function as BCs and use the static clock source selection mode to transmit clock signals to servers using 1588v2. PE1 and PE2 each are a stack of two member devices.

Figure 6-22 Clock synchronization networking

Configuration Roadmap

The configuration roadmap is as follows:

  1. Import external clock signals.

  2. Set the 1588v2 clock mode of devices on the network to BC because all the devices support 1588v2.

  3. Configure PE1 and PE2 as system master clocks and connect them to external clocks so that PE1 and PE2 back up each other.

  4. Configure multicast MAC encapsulation for 1588v2 messages and set the delay measurement mechanism to Delay.

Procedure

  1. Configure each of PE1 and PE2 as a stack. For details, see Example for Configuring a Stack (in MPU Connection Mode). In each stack, stack member ports are 10GE1/1/0/4, 10GE1/1/0/5, 10GE2/1/0/4, and 10GE2/1/0/5.
  2. Import external clock signals.

    # In the stack of PE1, set the clock link mode of stack member ports to interlink. The configuration of PE2 is similar to the configuration of PE1.
    <HUAWEI> system-view
    [~HUAWEI] sysname PE1
    [*HUAWEI] commit
    [~PE1] interface 10ge 1/1/0/4
    [~PE1-10GE1/1/0/4] clock link-mode interlink
    [*PE1-10GE1/1/0/4] commit
    [~PE1-10GE1/1/0/4] quit
    [~PE1] interface 10ge 1/1/0/5
    [~PE1-10GE1/1/0/5] clock link-mode interlink
    [*PE1-10GE1/1/0/5] commit
    [~PE1-10GE1/1/0/5] quit
    [~PE1] interface 10ge 2/1/0/4
    [~PE1-10GE2/1/0/4] clock link-mode interlink
    [*PE1-10GE2/1/0/4] commit
    [~PE1-10GE2/1/0/4] quit
    [~PE1] interface 10ge 2/1/0/5
    [~PE1-10GE2/1/0/5] clock link-mode interlink
    [*PE1-10GE2/1/0/5] commit
    [~PE1-10GE2/1/0/5] quit
    # Configure the stack of PE1 to receive external clock signals. The configuration of PE2 is similar to the configuration of PE1.
    [~PE1] clock bits-type chassis 1 bits0 2mhz
    [*PE1] clock source chassis 1 bits0 synchronization enable
    [*PE1] clock source chassis 1 bits0 priority 10
    [*PE1] clock source chassis 1 bits0 ssm prc
    [*PE1] clock bits-type chassis 1 bits1 1pps input
    [*PE1] clock tod protocol ubx
    [*PE1] ptp clock-source chassis 1 bits1 on
    [*PE1] interface 10ge 1/1/0/1
    [*PE1-10GE1/1/0/1] clock synchronization enable
    [*PE1-10GE1/1/0/1] quit
    [*PE1] interface 10ge 1/1/0/2
    [*PE1-10GE1/1/0/2] clock synchronization enable
    [*PE1-10GE1/1/0/2] quit
    [*PE1] commit
    # Configure the stack of CE1 to receive external clock signals. The configuration of CE2 is similar to the configuration of CE1.
    <HUAWEI> system-view
    [~HUAWEI] sysname CE1
    [*HUAWEI] commit
    [~CE1] interface 10ge 1/0/2
    [~CE1-10GE1/0/2] clock synchronization enable
    [*CE1-10GE1/0/2] clock priority 10
    [*CE1-10GE1/0/2] clock ssm prc
    [*CE1-10GE1/0/2] quit
    [*CE1] interface 10ge 1/0/1
    [*CE1-10GE1/0/1] clock synchronization enable
    [*CE1-10GE1/0/1] quit
    [*CE1] commit
    

  3. Enable PTP globally and set the 1588v2 clock mode of devices on the network to BC.

    # Configure PE1. The configurations of PE2, CE1, and CE2 are similar to the configuration of PE1.

    [~PE1] ptp enable
    [*PE1] ptp device-type bc
    [*PE1] commit
    

  4. Enable PTP on interfaces.

    # Configure PE1. The configurations of PE2, CE1, and CE2 are similar to the configuration of PE1.

    [~PE1] interface 10ge 1/1/0/1
    [~PE1-10GE1/1/0/1] ptp delay-mechanism delay
    [*PE1-10GE1/1/0/1] ptp enable
    [*PE1-10GE1/1/0/1] quit
    [*PE1] interface 10ge 1/1/0/2
    [*PE1-10GE1/1/0/2] ptp delay-mechanism delay
    [*PE1-10GE1/1/0/2] ptp enable
    [*PE1-10GE1/1/0/2] quit

  5. Configure the static 1588v2 interface status.

    # Configure PE1.

    [~PE1] ptp set-port-state enable
    [*PE1] interface 10ge 1/1/0/1
    [*PE1-10GE1/1/0/1] ptp port-state master
    [*PE1-10GE1/1/0/1] quit
    [*PE1] interface 10ge 1/1/0/2
    [*PE1-10GE1/1/0/2] ptp port-state master
    [*PE1-10GE1/1/0/2] quit

    # Configure PE2.

    [~PE2] ptp set-port-state enable
    [*PE2] interface 10ge 1/1/0/1
    [*PE2-10GE1/1/0/1] ptp port-state slave
    [*PE2-10GE1/1/0/1] quit
    [*PE2] interface 10ge 1/1/0/2
    [*PE2-10GE1/1/0/2] ptp port-state master
    [*PE2-10GE1/1/0/2] quit

    # Configure CE1.

    [~CE1] ptp set-port-state enable
    [*CE1] interface 10ge 1/0/1
    [*CE1-10GE1/0/1] ptp port-state master
    [*CE1-10GE1/0/1] quit
    [*CE1] interface 10ge 1/0/2
    [*CE1-10GE1/0/2] ptp port-state slave
    [*CE1-10GE1/0/2] quit
    [*CE1] commit
    

    # Configure CE2.

    [~CE2] ptp set-port-state enable
    [*CE2] interface 10ge 1/0/1
    [*CE2-10GE1/0/1] ptp port-state slave
    [*CE2-10GE1/0/1] quit
    [*CE2] interface 10ge 1/0/2
    [*CE2-10GE1/0/2] ptp port-state master
    [*CE2-10GE1/0/2] quit
    [*CE2] commit
    

  6. Verify the configuration.

    # CE1 and CE2 can trace time information of PE1 and PE2. If you run the display ptp all command on CE1, for example, you can view PTP synchronization information.

    [~CE1] display ptp all
      Device config info                                                            
      ------------------------------------------------------------------------------
      PTP state         :enabled            Domain  value      :0                 
      Slave only        :no                   Device type        :BC                
      Set port state    :yes                  Local clock ID     :00259e1000000001  
      Acl               :no                   Virtual clock ID   :no               
      Acr               :no                   Time lock success  :yes               
      Asymmetry measure :disable              Passive measure    :disable           
                                                                                    
      BMC run info                                                                  
      ------------------------------------------------------------------------------
      Grand clock ID    :00259e1000000002                                           
      Receive number    :10GE1/0/2                                                  
      Parent clock ID   :00259e1000000002                                           
      Parent portnumber :4126                                                       
      Priority1         :110                 Priority2           :110               
      Step removed      :1                   Clock accuracy      :0x31              
      Clock class       :6                   Time Source         :0xa0              
      UTC Offset        :35                  UTC Offset Valid    :False             
      Timescale         :ARB                 Time traceable      :False             
      Leap              :None                Frequency traceable :False             
      Offset scaled     :0xffff                                                     
                                                                                    
      Port info                                                                     
      Name                        State        Delay-mech Ann-timeout Type   Domain 
      ------------------------------------------------------------------------------
      10GE1/0/1                   master       delay      4           BC     0      
      10GE1/0/2                   slave        delay      4           BC     0      
                                                                                      
      Time Performance Statistics(ns): Slot 1  Card 0  Port 1                       
      ------------------------------------------------------------------------------
      Realtime(T2-T1)   :140                     Pathdelay     :0                   
      Max(T2-T1)        :3510286792100                                              
      Min(T2-T1)        :-5715158684                                                
                                                                                    
      Clock source info                                                             
      Clock       Pri1 Pri2 Accuracy Class TimeSrc Signal Switch Direction In-Status
      ------------------------------------------------------------------------------
      local       128  128  0x31     187   0xa0    -      -      -         -        

    # The following uses PE1 as an example. Run the display clock cluster frequency source and display clock cluster time source commands to check synchronization information of a stack.

    [~PE1] display clock cluster frequency source
    Chassis                                                                         
      Chassis   Trace-state   Pull-in   Trace-source                  Lock           
    --------------------------------------------------------------------------      
      1         lock          into      --                            yes            
      2         lock          into      10GE2/1/0/1                    yes            
                                                                                    
    Port                                                                            
      Source                        Peer Port                      State               
    ----------------------------------------------------------------------          
      10GE1/1/0/1                   10GE2/1/0/1                    normal              
      10GE1/1/0/2                   10GE2/1/0/2                    normal              
      10GE2/1/0/1                   10GE1/1/0/1                    normal              
      10GE2/1/0/2                   10GE1/1/0/2                    normal              
    [~PE1] display clock cluster time source
    Chassis                                                                         
      Chassis   Trace-source                  Lock                                   
    --------------------------------------------------                              
      1         --                            yes                                    
      2         10GE2/1/0/1                    yes                                    
                                                                                    
    Port                                                                            
      Source                        Peer Port                      In-Status           
    ----------------------------------------------------------------------          
      10GE1/1/0/1                    10GE2/1/0/1                    normal              
      10GE1/1/0/2                    10GE2/1/0/2                    normal              
      10GE2/1/0/1                    10GE1/1/0/1                    normal              
      10GE2/1/0/2                    10GE1/1/0/2                    normal              

Configuration Files

  • CE1 configuration file

    #
    sysname CE1
    #
    ptp enable
    ptp device-type bc
    ptp set-port-state enable
    #
    interface 10GE1/0/1
     clock synchronization enable
     ptp port-state master
     ptp enable
    #
    interface 10GE1/0/2
     clock synchronization enable
     clock priority 10
     clock ssm prc
     ptp port-state slave
     ptp enable
    #
    return  
    
  • CE2 configuration file

    #
    sysname CE2
    #
    ptp enable
    ptp device-type bc
    ptp set-port-state enable
    #
    interface 10GE1/0/1
     clock synchronization enable
     clock priority 10
     clock ssm prc
     ptp port-state slave
     ptp enable
    #
    interface 10GE1/0/2
     clock synchronization enable
     ptp port-state master
     ptp enable
    #
    return  
    
  • PE1 configuration file

    #
    sysname PE1
    #
    ptp enable
    ptp device-type bc
    ptp clock-source bits1 on slot 1
    ptp set-port-state enable
    #
    clock source bits0 synchronization enable slot clc1/5                          
    clock source bits0 priority 10 slot clc1/5                                     
    clock source bits0 ssm prc slot clc1/5
    clock bits-type bits0 2mhz slot clc1/5
    clock bits-type bits1 1pps input slot clc1/5
    
    interface Stack-Port1/1
    #
    interface Stack-Port2/1
    #
    interface 10GE1/1/0/1
     clock synchronization enable
     ptp port-state master
     ptp enable
    #
    interface 10GE1/1/0/2
     clock synchronization enable
     ptp port-state master
     ptp enable
    #
    interface 10GE1/1/0/4
     port mode stack
     stack-port 1/1
     clock link-mode interlink
    #
    interface 10GE1/1/0/5
     port mode stack
     stack-port 1/1
     clock link-mode interlink
    #
    interface 10GE2/1/0/4
     port mode stack
     stack-port 2/1
     clock link-mode interlink
    #
    interface 10GE2/1/0/5
     port mode stack
     stack-port 2/1
     clock link-mode interlink
    #
    return
  • PE2 configuration file

    #
    sysname PE2
    #
    ptp enable
    ptp device-type bc
    ptp clock-source bits1 on slot 1
    ptp set-port-state enable
    #
    clock source bits0 synchronization enable slot clc1/5                          
    clock source bits0 priority 10 slot clc1/5                                     
    clock source bits0 ssm prc slot clc1/5
    clock bits-type bits0 2mhz slot clc1/5
    clock bits-type bits1 1pps input slot clc1/1
    
    interface Stack-Port1/1
    #
    interface Stack-Port2/1
    #
    interface 10GE1/1/0/1
     clock synchronization enable
     ptp port-state slave
     ptp enable
    #
    interface 10GE1/1/0/2
     clock synchronization enable
     ptp port-state master
     ptp enable
    #
    interface 10GE1/1/0/4
     port mode stack
     stack-port 1/1
     clock link-mode interlink
    #
    interface 10GE1/1/0/5
     port mode stack
     stack-port 1/1
     clock link-mode interlink
    #
    interface 10GE2/1/0/4
     port mode stack
     stack-port 2/1
     clock link-mode interlink
    #
    interface 10GE2/1/0/5
     port mode stack
     stack-port 2/1
     clock link-mode interlink
    #
    return
Translation
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Updated: 2019-04-20

Document ID: EDOC1100074722

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