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Configuration Guide - Device Management

CloudEngine 8800, 7800, 6800, and 5800 V200R005C10

This document describes the configurations of Device Management, including device status query, hardware management, Information Center Configuration, NTP, Synchronous Ethernet Configuration, Fault Management Configuration, Energy-Saving Management Configuration, Performance Management Configuration, Maintenance Assistant Configuration, and OPS Configuration.
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Huawei uses machine translation combined with human proofreading to translate this document to different languages in order to help you better understand the content of this document. Note: Even the most advanced machine translation cannot match the quality of professional translators. Huawei shall not bear any responsibility for translation accuracy and it is recommended that you refer to the English document (a link for which has been provided).
Example for Configuring Clock Synchronization on a Ring Network

Example for Configuring Clock Synchronization on a Ring Network

Networking Requirements

In Figure 5-14, devices on the ring clock synchronization network are connected to each other. To ensure reliability of the clock synchronization network, Device1 and Device3 each are connected to an external clock source to import clock signals. During network deployment, each device preferentially traces clock signals sent from Device1. When the clock source connected to Device1 is faulty, devices trace clock signals sent from Device3.

To ensure that the devices trace best-quality clock signals, enable these devices to select clock sources based on SSM quality levels.

Figure 5-14 Configuring clock synchronization on a ring network
Table 5-2 Clock source priority and SSM quality level of each device

Device

Clock Source in Use

Priority

SSM Quality Level

Device1

10GE1/0/1

2

-

10GE1/0/2

-

-

10GE1/0/3

1

ssua

Device2

10GE1/0/1

1

-

10GE1/0/2

2

-

Device3

10GE1/0/1

-

-

10GE1/0/2

3

-

10GE1/0/3

1

ssub

Device4

10GE1/0/1

1

-

10GE1/0/2

2

-

Configuration Roadmap

The configuration roadmap is as follows:

  1. Configure clock sources.
  2. Configure automatic clock source selection and configure SSM quality levels for clock source selection.
  3. Simulate a fault of the external clock connected to Device1 to check whether the devices can trace clock signals sent from the external clock connected to Device3.

Procedure

  1. Configure clock sources.

    # Configure Device1.
    <HUAWEI> system-view
    [~HUAWEI] sysname Device1
    [*HUAWEI] commit
    [~Device1] interface 10ge 1/0/1
    [~Device1-10GE1/0/1] clock synchronization enable
    [*Device1-10GE1/0/1] clock priority 2
    [*Device1-10GE1/0/1] commit
    [~Device1-10GE1/0/1] quit
    [~Device1] interface 10ge 1/0/2
    [~Device1-10GE1/0/2] clock synchronization enable
    [*Device1-10GE1/0/2] commit
    [~Device1-10GE1/0/2] quit
    [~Device1] interface 10ge 1/0/3
    [~Device1-10GE1/0/3] clock synchronization enable
    [~Device1-10GE1/0/3] clock ssm ssua
    [*Device1-10GE1/0/3] clock priority 1
    [*Device1-10GE1/0/3] commit
    [~Device1-10GE1/0/3] quit
    # Configure Device2. The configuration of Device4 is similar to the configuration of Device2 and is not mentioned here.
    <HUAWEI> system-view
    [~HUAWEI] sysname Device2
    [*HUAWEI] commit
    [~Device2] interface 10ge 1/0/1
    [~Device2-10GE1/0/1] clock synchronization enable
    [*Device2-10GE1/0/1] clock priority 1
    [*Device2-10GE1/0/1] commit
    [~Device2-10GE1/0/1] quit
    [~Device2] interface 10ge 1/0/2
    [~Device2-10GE1/0/2] clock synchronization enable
    [*Device2-10GE1/0/2] clock priority 2
    [*Device2-10GE1/0/2] commit
    [~Device2-10GE1/0/2] quit
    # Configure Device3.
    <HUAWEI> system-view
    [~HUAWEI] sysname Device3
    [*HUAWEI] commit
    [~Device3] interface 10ge 1/0/1
    [~Device3-10GE1/0/1] clock synchronization enable
    [*Device3-10GE1/0/1] commit
    [~Device3-10GE1/0/1] quit
    [~Device3] interface 10ge 1/0/2
    [~Device3-10GE1/0/2] clock synchronization enable
    [*Device3-10GE1/0/2] clock priority 3
    [*Device3-10GE1/0/2] commit
    [~Device3-10GE1/0/2] quit
    [~Device3] interface 10ge 1/0/3
    [~Device3-10GE1/0/3] clock synchronization enable
    [*Device3-10GE1/0/3] clock ssm ssub
    [*Device3-10GE1/0/3] clock priority 1
    [*Device3-10GE1/0/3] commit
    [~Device3-10GE1/0/3] quit

  2. Configure automatic clock source selection and configure SSM quality levels for clock source selection.

    # Configure Device1. The configurations of other devices are similar to the configuration of Device1 and are not mentioned here.

    [~Device1] clock clear         //If a clock source has been manually or forcibly specified, running this command will restore automatic clock source selection. Otherwise, this step is not required.
    [~Device1] clock ssm-control on
    [*Device1] clock run-mode normal
    [*Device1] commit

  3. Verify the configuration.

    Run the display clock source command on Device1, Device2, Device3, and Device4 to check the clock source traced by the system clock and status of each clock source.

    # Check the clock source traced by the system clock and status of each clock source on Device1.

    [~Device1] display clock source
      System trace source State:   lock mode            
                                   into pull-in range   
      Current system trace source: 10GE1/0/3            
      Frequency lock success:      yes                  
    
      Master board
      Source        Pri(sys)   In-SSM   Out-SSM   State          Ref-Source
      ------------------------------------------------------------------------------
      10GE1/0/1     2          dnu      ssua      normal         yes
      10GE1/0/3     1          ssua     --        normal         yes

    # Check the clock source traced by the system clock and status of each clock source on Device2.

    [~Device2] display clock source
      System trace source State:   lock mode            
                                   into pull-in range   
      Current system trace source: 10GE1/0/1            
      Frequency lock success:      yes                  
    
      Master board
      Source        Pri(sys)   In-SSM   Out-SSM   State          Ref-Source
      ------------------------------------------------------------------------------
      10GE1/0/1     1          ssua     dnu       normal         yes
      10GE1/0/2     2          dnu      ssua      normal         yes

    # Check the clock source traced by the system clock and status of each clock source on Device3.

    [~Device3] display clock source
      System trace source State:   lock mode            
                                   into pull-in range   
      Current system trace source: 10GE1/0/2            
      Frequency lock success:      yes                  
    
      Master board
      Source        Pri(sys)   In-SSM   Out-SSM   State          Ref-Source
      ------------------------------------------------------------------------------
      10GE1/0/1     ---        dnu      ssua      normal         no 
      10GE1/0/2     3          ssua     dnu       normal         yes
      10GE1/0/3     1          ssub     ssua      normal         yes

    # Check the clock source traced by the system clock and status of each clock source on Device4.

    [~Device4] display clock source
      System trace source State:   lock mode            
                                   into pull-in range   
      Current system trace source: 10GE1/0/1            
      Frequency lock success:      yes                  
    
      Master board
      Source        Pri(sys)   In-SSM   Out-SSM   State          Ref-Source
      ------------------------------------------------------------------------------
      10GE1/0/1     1          ssua     dnu       normal         yes
      10GE1/0/2     2          dnu      ssua      normal         yes

  4. Modify the SSM quality level of the external clock on Device1. Run the display clock source command on Device1, Device2, Device3, and Device4 to check the clock source traced by the system clock and status of each clock source.

    [~Device1] interface 10ge 1/0/3
    [~Device1-10GE1/0/3] clock ssm sec
    [*Device1-10GE1/0/3] commit

    # Run the display clock source command on Device1. The command output shows that Device1 has traced the clock signals sent from Device3.

    [~Device1] display clock source
      System trace source State:   lock mode            
                                   into pull-in range   
      Current system trace source: 10GE1/0/1            
      Frequency lock success:      yes                  
    
      Master board
      Source        Pri(sys)   In-SSM   Out-SSM   State          Ref-Source
      ------------------------------------------------------------------------------
      10GE1/0/1     2          ssub     dnu       normal         yes
      10GE1/0/3     1          sec      --        normal         yes

    # Run the display clock source command on Device2. The command output shows that Device2 has traced the clock signals sent from Device3.

    [~Device2] display clock source
      System trace source State:   lock mode            
                                   into pull-in range   
      Current system trace source: 10GE1/0/2            
      Frequency lock success:      yes                  
    
      Master board
      Source        Pri(sys)   In-SSM   Out-SSM   State          Ref-Source
      ------------------------------------------------------------------------------
      10GE1/0/1     1          dnu      ssub      normal         yes
      10GE1/0/2     2          ssub     dnu       normal         yes

    # Run the display clock source command on Device3. The command output shows that Device3 has traced the clock signals sent from its connected BITS clock.

    [~Device3] display clock source
      System trace source State:   lock mode            
                                   into pull-in range   
      Current system trace source: 10GE1/0/3           
      Frequency lock success:      yes                  
    
      Master board
      Source        Pri(sys)   In-SSM   Out-SSM   State          Ref-Source
      ------------------------------------------------------------------------------
      10GE1/0/1     ---        dnu      ssub      normal         no 
      10GE1/0/2     3          dnu      ssub      normal         yes
      10GE1/0/3     1          ssub     dnu       normal         yes

    # Run the display clock source command on Device4. The command output shows that Device4 has traced the clock signals sent from Device3.

    [~Device4] display clock source
      System trace source State:   lock mode            
                                   into pull-in range   
      Current system trace source: 10GE1/0/1            
      Frequency lock success:      yes                  
    
      Master board
      Source        Pri(sys)   In-SSM   Out-SSM   State          Ref-Source
      ------------------------------------------------------------------------------
      10GE1/0/1     1          ssub     dnu       normal         yes
      10GE1/0/2     2          dnu      ssub      normal         yes

Configuration Files

  • Device1 configuration file

    #
    sysname Device1
    #
    clock ssm-control on
    #
    interface 10GE1/0/1
     clock synchronization enable
     clock priority 2
    #
    interface 10GE1/0/2
     clock synchronization enable
    #
    interface 10GE1/0/3
     clock synchronization enable
     clock priority 1
     clock ssm ssua 
    #
    return
  • Device2 configuration file

    #
    sysname Device2
    #
    clock ssm-control on
    #
    interface 10GE1/0/1
     clock synchronization enable
     clock priority 1
    #
    interface 10GE1/0/2
     clock synchronization enable
     clock priority 2
    #
    return
  • Device3 configuration file

    #
    sysname Device3
    #
    clock ssm-control on
    #
    interface 10GE1/0/1
     clock synchronization enable
    #
    interface 10GE1/0/2
     clock synchronization enable
     clock priority 3
    #
    interface 10GE1/0/3
     clock synchronization enable
     clock priority 1
     clock ssm ssub 
    #
    return
  • Device4 configuration file

    #
    sysname Device4
    #
    clock ssm-control on
    #
    interface 10GE1/0/1
     clock synchronization enable
     clock priority 1
    #
    interface 10GE1/0/2
     clock synchronization enable
     clock priority 2
    #
    return
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Updated: 2019-04-20

Document ID: EDOC1100075362

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