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Configuration Guide - Device Management

CloudEngine 8800, 7800, 6800, and 5800 V200R005C10

This document describes the configurations of Device Management, including device status query, hardware management, Information Center Configuration, NTP, Synchronous Ethernet Configuration, Fault Management Configuration, Energy-Saving Management Configuration, Performance Management Configuration, Maintenance Assistant Configuration, and OPS Configuration.
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Huawei uses machine translation combined with human proofreading to translate this document to different languages in order to help you better understand the content of this document. Note: Even the most advanced machine translation cannot match the quality of professional translators. Huawei shall not bear any responsibility for translation accuracy and it is recommended that you refer to the English document (a link for which has been provided).
Time Synchronization Implementation

Time Synchronization Implementation

In 1588v2 time synchronization, the master and slave nodes exchange time synchronization packets and calculate the total round-trip delay between two nodes based on the timestamps of the received and sent packets. This implementation is similar to NTP. If the delays in the two directions are the same, one-way delay is half of the total round-trip delay. Therefore, the time difference between the slave and master nodes can be obtained. The slave node adjusts the local time according to the time difference to implement time synchronization with the master node. 1588v2 differs from NTP:
  • NTP often runs on MPUs to measure the communications delay, including the link delay and delays caused by various internal processings such as internal congestion queuing, software scheduling, and software processing. The high delay and jitter result in low time synchronization accuracy.
  • 1588v2 assumes that the link delay is a constant value (or a trivial value that can be ignored between two time synchronization processes) and bidirectional delays along a link are the same. In 1588v2, the link delay can be measured based on the timestamps on the link ingress and egress to achieve high time synchronization accuracy.
1588v2 defines two modes for delay measurement and time synchronization:
  • Delay mode: measures the end-to-end delay.
  • Peer Delay (Pdelay) mode: calculates the transmission time (link delay) between two communication ports that support the Pdelay mechanism. This mechanism is irrelevant to master and slave states of ports.

Delay Mode

Figure 6-8 shows the process of calculating the average link delay and time difference between the master and slave nodes in Delay mode.

Figure 6-8 Delay mode

NOTE:
  • The devices timestamp messages based on their system clocks when these messages leave and arrive at the devices.
  • In one-step mode, a Sync message in Delay mode carries the timestamp when it is sent.
  • In two-step mode, a Sync message in Delay mode does not carry the timestamp when it is sent. Devices record the time when the Sync message is sent, and a subsequent Follow_Up message carries the timestamp when the Sync message is sent.
  1. The master device sends a Sync message at t1. If the master device works in one-step mode, t1 is sent to the slave device through the Sync message. If the master device works in two-step mode, t1 is sent to the slave device through the subsequent Follow_Up message.
  2. In one-step mode, the slave device receives the Sync message at t2 and obtains t1 from the Sync message. In two-step mode, the slave device receives the Sync message at t2 and obtains t1 from the Follow_Up message.
  3. The slave device sends a Delay_Req message to the master device at t3.
  4. The master device receives the Delay_Req message at t4.
  5. The master device sends a Delay_Resp message recording t4 to the slave device.
Based on the preceding four timestamps, t1, t2, t3, and t4, the slave device can calculate the average link delay and time difference between it and the master device to synchronize the time with the master device. The calculation process is as follows:
  1. Assume that time delay for sending packets from the master device to the slave device is Delayms, time delay for sending packets from the slave device to the master device is Delaysm, and time difference between the slave and master devices is Offset. The formula for the average link delay between the slave and master devices is: Delay = (Delayms + Delaysm)/2.
  2. Because t2 - t1 = Delayms + Offset and t4 - t3 = Delaysm - Offset, (t2 - t1) - (t4 - t3) = (Delayms + Offset) - (Delaysm - Offset).
  3. According to the preceding formula:
    • Delayms + Delaysm = (t2 - t1) + (t4 - t3)
    • Offset = [(t2 - t1) - (t4 - t3) -(Delayms - Delaysm)]/2
  4. If bidirectional link delays between the master and slave devices are symmetric or Delayms equals Delaysm, the following formulas can be used to calculate the average link delay and time difference between the two devices:
    • Delay = [(t2 - t1) + (t4 - t3)]/2
    • Offset = [(t2 - t1) - (t4 - t3)]/2

In Figure 6-9, the time difference between the local clock and current time is calculated using 1588v2, and then the local clock is adjusted based on the time difference. This synchronization process is performed repeatedly to ensure time synchronization between the slave and master devices.

Figure 6-9 Time Correction

1588v2 time synchronization requires symmetric bidirectional path delays between the master and slave devices. If bidirectional path delays are asymmetric, a synchronization offset is introduced. The offset is half of the difference between bidirectional path delays. 1588v2 high-precision time synchronization requires that the delay between the two nodes be stable and no jitter occur. The link delay generally meets this requirement, but the forwarding delay and jitter of devices are large. Therefore, in IEEE 1588v2, the correction field (for delay correction) needs to be used in the time synchronization calculation in Delay mode to obtain the correct average path delay and time offset.

Figure 6-10 Forwarding delay correction process

In Figure 6-10, the device modifies the correction field of an 1588v2 message at the inbound and outbound interfaces: subtracts the timestamp of the current time at the inbound interface, and adds the timestamp of the current time at the outbound interface. That is, the device adds the forwarding delay of the message within the local device to the correction field. In IEEE 1588v2, the process of calculating the average path delay by using the Delay mechanism that uses forwarding delay correction is as follows:

  1. The master node sends a Sync message to the slave node. The message carries the correction field CF1 containing the forwarding delay generated when the message passes through the master node. When the slave node receives the Sync message and performs time synchronization calculation, it subtracts the CF1. There is only the link delay.
    NOTE:

    In two-step mode, the slave node also needs to subtract the correction field from the Follow_Up message during time synchronization calculation.

  2. The slave node sends a Delay_Req message to the master node. The message carries the correction field containing the forwarding delay of the slave node.
  3. After receiving the Delay_Req message, the master node calculates a new correction field and adds the correction field of the message to the new correction field to form CF2.
  4. The master node sends a Delay_Resp message carrying CF2 to the slave node.
  5. After receiving the Delay_Resp message, the slave node performs time synchronization calculation and subtracts the correction field that contains the forwarding delay. The following lists the formulas for calculating the correct delay and offset:
    • Delay = [(t2-t1-CF1) + (t4-t3-CF2)]/2 = [(t2-t1)+(t4-t3) – (CF1+CF2)]/2
    • Offset = [(t2 - t1-CF1) - (t4 - t3-CF2)] / 2 = [(t2-t1) – (t4-t3) – (CF1– CF2)]/2

In this way, high-precision time synchronization can be implemented.

Pdelay Mode

Figure 6-11 shows the process of calculating the average link delay and time difference between the master and slave nodes in Pdelay mode. This process is similar to that in Delay mode.

Figure 6-11 Pdelay mode
NOTE:
  • The devices timestamp messages based on their system clocks when these messages leave and arrive at the devices.
  • In Figure 6-11, tab and tba indicate bidirectional link delays, which are assumed to be the same.
  • In one-step mode, a Pdelay_Resp message in Pdelay mode carries the timestamp when it is sent.
  • In two-step mode, a Pdelay_Resp message in Pdelay mode does not carry the timestamp when it is sent. Devices record the time when the Pdelay_Resp message is sent, and a subsequent Pdelay_Resp_Follow_Up message carries the timestamp when the Pdelay_Resp message is sent.
  1. NodeA sends a Pdelay-Req message at t1.

  2. NodeB receives the Pdelay-Req message at t2 and obtains t1 from this message.

  3. NodeB sends a Pdelay_Resp message to NodeA at t3. If NodeB works in one-step mode, t3 and the time difference between t3 and t2 are sent to NodeA through the Pdelay_Resp message. If NodeB works in two-step mode, t3 and the time difference between t3 and t2 are sent to NodeA through the subsequent Pdelay_Resp_Follow_Up message.

  4. NodeA receives the Pdelay_Resp message at t4 and obtains t3 and the time difference between t3 and t2 from the Pdelay_Resp message in one-step mode or from the Pdelay_Resp_Follow_Up message in two-step mode.

Based on the preceding four timestamps, t1, t3, t4, and time difference between t3 and t2, the average link delay between NodeA and NodeB can be calculated using the following formula:

Delay = [(t4 - t1) - (t3 - t2)]/2

In the preceding process, the link delay is calculated and updated in real time, but time synchronization is not performed. Time synchronization requires the master and slave nodes to exchange Sync messages. The master node periodically sends Sync messages to the slave node, and the slave node corrects the delay based on the received Sync messages and obtains the time difference compared with the master node. Based on the time difference, the slave node adjusts its local time to synchronize with the master node.

Asymmetrical Delay Correction

1588v2 requires bidirectional delays of a link to be symmetric. In real-world applications, however, bidirectional delays of a link may be asymmetric. Asymmetric delays may be caused by link attributes or device attributes, for example, bidirectional link delays are different on the link segment from the location of a timestamp to the link. To address this issue, 1588v2 provides the asymmetric delay correction mechanism. Figure 6-12 shows this mechanism.

Figure 6-12 Asymmetric delay correction

Generally, tms equals tsm. If tms does not equal tsm, you can configure their time difference as the asymmetrical delay correction value as long as the delay difference is fixed and can be obtained in advance. During time synchronization, 1588v2 also calculates the asymmetrical delay correction value, improving time synchronization accuracy on links with asymmetric delays.

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Updated: 2019-04-20

Document ID: EDOC1100075362

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