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Atlas 200 Hardware Development Guide 02

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Huawei uses machine translation combined with human proofreading to translate this document to different languages in order to help you better understand the content of this document. Note: Even the most advanced machine translation cannot match the quality of professional translators. Huawei shall not bear any responsibility for translation accuracy and it is recommended that you refer to the English document (a link for which has been provided).
PCIe Interface

PCIe Interface

Table 4-1 PCB design requirements

Item

Design Requirement

Description

Rate

8 Gbps/125 ps

-

Topology

Point to point

-

Chip internal resistance

50 ohm

P/N ground resistance.

Transmission line impedance

Differential 85 ohm (tight coupling)

±10%, encapsulation impedance 85 ohm.

Routing layer

Inner layer

-

Reference plane

Ground plane (complete)

-

Differential pair spacing

6 h (inner layer) /11 h (surface layer)

H indicates the medium thickness of the reference plane.

TX/RX spacing requirement

Routing at different layers or 10h at the same layer

H indicates the medium thickness of the reference plane.

Distance from the differential pair to the reference plane/capacitor pad

3 h/4 h

H indicates the medium thickness of the reference plane.

PCB wiring length

2-7 inch (FR4) (line width: > 5 mil)

Df ≈ 0.023.

Differential pair skew (TX or RX)

50 mil

-

Differential pair NP skew

5 mil

-

Differential pair NP compensation

See the figure.

Reflow ground hole

Reflow ground holes added at changed layers

Symmetrically added.

Number of vias

≤ 4 (TX&RX)

Connector, AC capacitor, fanout.

Signal vias impedance continuity

It is recommended that the ground hole distance and signal antipad size be optimized based on simulation results.

Optimize the antipads of vias. For details, see the following figure.

Signal vias STUB length

≤ 16 mil

Signal vias non-functional pad

Removed

Signal vias layout

Symmetric

AC coupling capacitor

TX and RX required

There is no AC capacitor inside the module.

AC coupling capacitor position

Near the connector

-

AC coupling capacitor impedance continuity

The continuity is related to the cascading, capacitor packaging, and material. The reference layer is excavated. The size of the antipad must be appropriate. It is recommended that the antipad size be optimized by simulation.

Reference: 0402 capacitor

Connector pad impedance continuity

The continuity is related to the cascading, capacitor packaging, and material. It is recommended that the antipad size be optimized by simulation.

Reference clock

Single source

100 MHz, RC/EP reference clock source

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Updated: 2019-07-29

Document ID: EDOC1100079542

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