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Atlas 200 Hardware Development Guide 03

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Huawei uses machine translation combined with human proofreading to translate this document to different languages in order to help you better understand the content of this document. Note: Even the most advanced machine translation cannot match the quality of professional translators. Huawei shall not bear any responsibility for translation accuracy and it is recommended that you refer to the English document (a link for which has been provided).
USB Interface

USB Interface

Table 4-4 PCB design requirements

Item

Design Requirement

Description

Rate

5 Gbps/200 ps

USB 3.0.

Topology

Point to point

-

Chip internal resistance

90 ohm differential

TX&RX termination resistor on Die.

Transmission line impedance

Differential 90 ohm (tight coupling)

±10%, encapsulation impedance 90 ohm.

Routing layer

Inner layer

-

Reference plane

Ground plane (complete)

-

Differential pair spacing

6 h (inner layer) /11 h (surface layer)

H indicates the medium thickness of the reference plane.

TX/RX spacing requirement

Routing at different layers or 15h at the same layer

H indicates the medium thickness of the reference plane.

Distance from the differential pair to the reference plane/capacitor pad

3 h/4 h

H indicates the medium thickness of the reference plane.

Longest PCB routing

(BTB connector to USB connector)

3 inches

FR4, Df < 0.023, line width > 4 mil.

Differential pair skew (TX or RX)

Not required

-

Differential pair NP skew

5 mil

-

Differential pair NP compensation

See the figure

Reflow ground hole

Reflow ground holes added at changed layers

Symmetrically added.

Number of vias

≤ 4 (TX&RX)

Connector, AC capacitor, fanout

Signal vias STUB length

≤ 16 mil

-

Signal vias non-functional pad

Removed

-

Signal vias layout

Symmetric

-

AC coupling capacitor

RX

An AC capacitor has been added to the TX module.

AC capacitor position

Close to the common-mode inductor

ESD capacitance (capacitive)

0.8 pf (max)

-

ESD (position)

< 320 mil

Close to the connector

ESD reference PCB design

The reference layer is excavated to improve impedance continuity.

-

Common-mode inductor position

< 320 mil

Close to the AC capacitor and ESD

Common-mode inductor differential impedance

90 ohm

-

Common-mode inductor impedance @100 MHz

65 ohm/90 ohm

Min/Max

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Updated: 2019-11-18

Document ID: EDOC1100079542

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