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Atlas 200 Hardware Development Guide 03

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Huawei uses machine translation combined with human proofreading to translate this document to different languages in order to help you better understand the content of this document. Note: Even the most advanced machine translation cannot match the quality of professional translators. Huawei shall not bear any responsibility for translation accuracy and it is recommended that you refer to the English document (a link for which has been provided).
PCIe Interface

PCIe Interface

The Atlas 200 supports PCIe 3.0 and is backward compatible with PCIe 2.0 and PCIe 1.0. The main features of the Atlas 200 are as follows:

  • Supports RC or EP.
  • Provides one port with a maximum link of X4.
  • Supports TX DFE adaptation, including Preset and Coefficient.
  • Supports the reference clock spread spectrum or internal spread spectrum.
  • Supports different spread spectrum modes for CC, SSNS, and SRIS.
  • Supports different low-power modes for L0s/L1/L2 and does not support L1ss.
  • Supports lane reversal. (Only reversals of 0-3, 1-2, 2-1, and 3-0 are supported. Reversals of 0-2 and 1-3 are not supported.)
  • P/N polarity reversal.

Signal Design Requirements

Table 3-3 Signal design requirements

Pin Name

Function Description

PCIE_RX0_P/N

PCIe Lane 0 Receive P/N. The user PCB needs to be connected to a blocking capacitor. The 220 nF capacitor is recommended for PCIe 3.0, and 100 nF capacitor is recommended for PCIe 2.0/1.0.

PCIE_RX1_P/N

PCIe Lane 1 Receive P/N. The user PCB needs to be connected to a blocking capacitor. The 220 nF capacitor is recommended for PCIe 3.0, and 100 nF capacitor is recommended for PCIe 2.0/1.0.

PCIE_RX2_P/N

PCIe Lane 2 Receive P/N. The user PCB needs to be connected to a blocking capacitor. The 220 nF capacitor is recommended for PCIe 3.0, and 100 nF capacitor is recommended for PCIe 2.0/1.0.

PCIE_RX3_P/N

PCIe Lane 3 Receive P/N. The user PCB needs to be connected to a blocking capacitor. The 220 nF capacitor is recommended for PCIe 3.0, and 100 nF capacitor is recommended for PCIe 2.0/1.0.

PCIE_TX0_P/N

PCIe Lane 0 Transmit P/N. The user PCB needs to be connected to a blocking capacitor. The 220 nF capacitor is recommended for PCIe 3.0, and 100 nF capacitor is recommended for PCIe 2.0/1.0.

PCIE_TX1_P/N

PCIe Lane 1 Transmit P/N. The user PCB needs to be connected to a blocking capacitor. The 220 nF capacitor is recommended for PCIe 3.0, and 100 nF capacitor is recommended for PCIe 2.0/1.0.

PCIE_TX2_P/N

PCIe Lane 2 Transmit P/N. The user PCB needs to be connected to a blocking capacitor. The 220 nF capacitor is recommended for PCIe 3.0, and 100 nF capacitor is recommended for PCIe 2.0/1.0.

PCIE_TX3_P/N

PCIe Lane 3 Transmit P/N. The user PCB needs to be connected to a blocking capacitor. The 220 nF capacitor is recommended for PCIe 3.0, and 100 nF capacitor is recommended for PCIe 2.0/1.0.

PCIE_CLK_IN_P/N

In the RC/EP mode, the input of the PCIe PHY reference clock is 100 MHz and the interface is LVDS. You can determine the AC or DC coupling based on the clock interface type.

There is no external coupling requirement. The internal AC coupling has been implemented. No external impedance matching terminal is required. Ensure that the clock source is the same in the common clock architecture.

PCIE_EP_RC_FLAG

PCIe RC/EP mode selection. The high level and low level are configured for the user PCB. VBUCK8_1V8 is required for pull-up.

  • 1: EP mode
  • 0: RC mode

PCIE_PERST_N

By default, the pins are configured to monitor the reset status of the PCIe interface sent by the Host side. When initializing the PCIe EP device, the module software needs to determine the pin status (EP mode).

After the module is powered on, query the level status of the signal. If the level is high, perform the PCIe PHY initialization.

After the module is powered on, the software can configure this signal as the hot reset signal of the Ascend 310. The signal falling edge can reset the Ascend 310. The configuration is invalid after the module is powered off.

There is a 100 kΩ pull-up resistor inside the module. It can be floated when it is not used. The application scenario must be used together with the PCIe timing.

PCIE_CLKREQ_N

The PCIe clock signal is used with the user clock system.

  • In the RC mode, float the signal when it is not used.
  • In the EP mode, the module outputs data to the PCIe Host.
    • The output of low level indicates that the PCIe Host provides the reference clock.
    • The output of high level indicates that the PCIe Host disables the reference clock. Float the signal when it is not used.

There is no pull-up resistor inside the signal module. An external pull-up resistor needs to be installed on the user PCB. VBUCK8_1V8 is required for pull-up.

PCIE_PEWAKE_N

PCIe wakeup, active low. It is used to wake up the user PCB system when it enters the sleep mode.

There is no pull-up resistor inside the module. An external pull-up resistor needs to be installed on the user PCB. Float the signal when it is not used. VBUCK8_1V8 is required for pull-up.

Multiplexing function: POWER_STATE. A low power consumption state is sent to the HOST indicator module. When the Ascend 310 enters the sleep mode, set 0. When the Ascend 310 is in the working mode, set 1.

When the PCIe interface is not used, do as follows:

  • Ground the differential reference clock pin.
  • Float the TX differential pin.
  • Float or ground the RX differential pin.
  • Float other signals.
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Updated: 2019-11-18

Document ID: EDOC1100079542

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