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Atlas 200 Hardware Development Guide 03

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Huawei uses machine translation combined with human proofreading to translate this document to different languages in order to help you better understand the content of this document. Note: Even the most advanced machine translation cannot match the quality of professional translators. Huawei shall not bear any responsibility for translation accuracy and it is recommended that you refer to the English document (a link for which has been provided).
RGMI Interface

RGMI Interface

The Atlas 200 integrates a Reduced Gigabit Media Independent Interface (RGMII) controller. An external RGMII PHY chip is required. After the conversion, it can be connected to an RJ45 connector.

Signal Design Requirements

Table 3-4 Signal design requirements

Pin Name

Main Function

Function Description

MDC

MDC

MDIO interface clock output. A 33 Ω resistor is connected to the module.

MDIO

MDIO

MDIO interface data input/output signal. An external pull-up resistor of 4.7-10 kΩ is installed on the user PCB. VBUCK8_1V8 is required for pull-up.

GE_PHY_RST_N

GPIO71

Reset signal of the external GE PHY component, active low. It is recommended that the external 4.7-10 kΩ pull-up resistor be reserved on the user PCB. VBUCK8_1V8 is required for pull-up.

RGMII_RXD_EN

RXD_EN

RGMII interface RX data validity signal. It is recommended that a 33 Ω resistor be connected.

RGMII_RXD_CLK

RXD_CLK

RGMII RX clock. It is recommended that a 33 Ω resistor be connected.

RGMII_RXD3

RXD3

RGMII RX data 3. It is recommended that a 33 Ω resistor be connected.

RGMII_RXD2

RXD2

RGMII RX data 2. It is recommended that a 33 Ω resistor be connected.

RGMII_RXD1

RXD1

RGMII RX data 1. It is recommended that a 33 Ω resistor be connected.

RGMII_RXD0

RXD0

RGMII RX data 0. It is recommended that a 33 Ω resistor be connected.

RGMII_TXD_EN

TXD_EN

RGMII interface TX data validity signal. A 33 Ω resistor has been connected in the module.

RGMII_TXD_CLK

TXD_CLK

RGMII TX clock. A 33 Ω resistors has been connected in the module.

RGMII_TXD3

TXD3

RGMII TX data 3. A 33 Ω resistor has been connected in the module.

RGMII_TXD2

TXD2

RGMII TX data 2. A 33 Ω resistor has been connected in the module.

RGMII_TXD1

TXD1

RGMII TX data 1. A 33 Ω resistor has been connected in the module.

RGMII_TXD0

TXD0

RGMII TX data 0. A 33 Ω resistor has been connected in the module.

GE_PHY_INT

PHY_INT

GE PHY interrupts input. The GPIO interrupt mode supports edge trigger (rising edge and falling edge), level trigger, and grouping.

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Updated: 2019-11-18

Document ID: EDOC1100079542

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