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TaiShan Server BIOS Parameter Reference (Kunpeng 920 Processor) 21
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PCIe Config

PCIe Config

This section describes how to control PCIe ports on the PCIe Config screen.

The PCIe Config screen is used to configure the PCIe controller and link parameters as well as display status of each processor to control PCIe ports, such as enabling the PCIe port, selecting the connection rate, and configuring parameters such as the Max Payload Size parameter. Figure 1 or Figure 2 shows the PCIe Config screen. Table 4-14 describes the parameters on the screen.

The PCIe Config screen varies according to the server or BIOS version. For details, see Table 4-14.

Figure 4-19 PCIe Config screen 1
Figure 4-20 PCIe Config screen 2
Figure 4-21 PCIe Config screen 3
Table 4-14 Parameters on the PCIe Config screen

Parameter

Description

Default Value

CPU 0 PCIe Configuration

Sets the PCIe parameters of the PCIe port on CPU 0.

N/A

CPU 1 PCIe Configuration

Sets the PCIe parameters of the PCIe port on CPU 1.

NOTE:

TaiShan 200 servers (models 2180 and 5180) do not support this parameter.

N/A

CPU 2 PCIe Configuration

Sets the PCIe parameters of the PCIe port on CPU 2.

NOTE:

This parameter is supported by TaiShan 200 servers (model 2480) and TaiShan 200 Pro servers (model 2480).

N/A

CPU 3 PCIe Configuration

Sets the PCIe parameters of the PCIe port on CPU 3.

NOTE:

This parameter is supported only by TaiShan 200 servers (model 2480) and TaiShan 200 Pro servers (model 2480).

N/A

Support DPC

Enables or disables the Deferred Procedure Call (DPC) function. The options are as follows:

  • Enable
  • Disable

Disable

SRIOV

Enables or disables Single Root Input/Output Virtualization (SRIOV). The options are as follows:

  • Enable
  • Disable

Enable

PCIe DSM5# Mode

Provides an advanced configuration and power interface (ACPI) to notify the OS kernel whether to reconfigure PCIe device resources. The options are as follows:

  • BIOS Reserve: use PCIe resources defined by the BIOS
  • Kernel Reserve: The OS can ignore the PCIe resource settings in the BIOS phase and reconfigure the PCIe resources.
NOTE:

This parameter is not supported by TaiShan 200 servers (models XA320, XA320C, and 2480) or TaiShan 200 Pro servers (model 2480).

BIOS Reserve

PCIe Port Control Policy

Specifies the PCIe port control policy. The options are as follows:

  • Auto
  • Compatible
NOTE:

Only the BIOSs on the following servers support this parameter:

  • BIOS V163 and later and V151 on TaiShan 200 servers (models 2280 and 5280)
  • All BIOS versions on TaiShan 200 Pro servers (model 2280) configured with Kunpeng 920 7265 or 5255 processors

Auto

NVMe GEN4 Disk Workaround

Enables or disables the performance optimization function of the NVMe Gen4 drive. Adjust the FC_Update parameter to improve the read performance of the NVMe Gen4 drive. The options are as follows:

  • Enable
  • Disable
NOTE:

Only the BIOSs on the following servers support this parameter:

  • BIOS V172 and later on TaiShan 200 servers (models 1280, 2180, 2280E, 2280, 2280VF, and 5280)
  • BIOS V322 and later on TaiShan 200 servers (models 2280VE, 5280VE, 5290, and 2480)
  • All BIOS versions on TaiShan 200 Pro servers (models 2480, 2280, and 1280)

Disable

SR-IOV System Page Size

Specifies the SR-IOV system page size of the BIOS. When the BIOS allocates SR-IOV resources, it aligns pages based on the value of this field. It is recommended that the value of this field be the same as the value of the OS kernel page size. The options are as follows:

  • 4K
  • 64K
NOTE:

Only the BIOSs on the following servers support this parameter:

  • BIOS V180 and later on TaiShan 200 servers (models 2280, 5280, 1280, 2180, 5180, 2480, 5290, and 2280E)
  • All BIOS versions on TaiShan 200 Pro servers (models 1280, 2280, and 2480)

4K

Slot1 BandWidth Splitting

Splits the bandwidth of slot 1 on riser card 1. The options are as follows:

  • Disable: Do not split.
  • X2: Split by X2.
  • X4: Split by X4.
  • X8: Split by X8.
NOTE:

Only the BIOSs on the following servers support this parameter:

  • BIOS V198 or later on TaiShan 200 servers (models 2280 and 2280K) equipped with Kunpeng 920 7260, 5250, or 5230 processors
  • BIOS V198 or later on TaiShan 200 servers (models 2280, 2280K, 5280, 5280K, and 2280_DEF) equipped with Kunpeng 920 5220 or 3210 processors

Disable

Slot2 BandWidth Splitting

Splits the bandwidth of slot 2 on riser card 1. The options are as follows:

  • Disable: Do not split.
  • X2: Split by X2.
  • X4: Split by X4.
  • X8: Split by X8.
NOTE:

Only the BIOSs on the following servers support this parameter:

  • BIOS V198 or later on TaiShan 200 servers (models 2280 and 2280K) equipped with Kunpeng 920 7260, 5250, or 5230 processors
  • BIOS V198 or later on TaiShan 200 servers (models 2280, 2280K, 5280, 5280K, and 2280_DEF) equipped with Kunpeng 920 5220 or 3210 processors

Disable

Slot3 BandWidth Splitting

Splits the bandwidth of slot 3 on riser card 1. The options are as follows:

  • Disable: Do not split.
  • X2: Split by X2.
  • X4: Split by X4.
  • X8: Split by X8.
NOTE:

Only the BIOSs on the following servers support this parameter:

  • BIOS V198 or later on TaiShan 200 servers (models 2280 and 2280K) equipped with Kunpeng 920 7260, 5250, or 5230 processors
  • BIOS V198 or later on TaiShan 200 servers (models 2280, 2280K, 5280, 5280K, and 2280_DEF) equipped with Kunpeng 920 5220 or 3210 processors

Disable

Slot4 BandWidth Splitting

Splits the bandwidth of slot 1 on riser card 2. The options are as follows:

  • Disable: Do not split.
  • X2: Split by X2.
  • X4: Split by X4.
  • X8: Split by X8.
NOTE:

Only the BIOSs on the following servers support this parameter:

  • BIOS V198 or later on TaiShan 200 servers (models 2280 and 2280K) equipped with Kunpeng 920 7260, 5250, or 5230 processors
  • BIOS V198 or later on TaiShan 200 servers (models 2280, 2280K, 5280, 5280K, and 2280_DEF) equipped with Kunpeng 920 5220 or 3210 processors

Disable

Slot5 BandWidth Splitting

Splits the bandwidth of slot 2 on riser card 2. The options are as follows:

  • Disable: Do not split.
  • X2: Split by X2.
  • X4: Split by X4.
  • X8: Split by X8.
NOTE:

Only the BIOSs on the following servers support this parameter:

  • BIOS V198 or later on TaiShan 200 servers (models 2280 and 2280K) equipped with Kunpeng 920 7260, 5250, or 5230 processors
  • BIOS V198 or later on TaiShan 200 servers (models 2280, 2280K, 5280, 5280K, and 2280_DEF) equipped with Kunpeng 920 5220 or 3210 processors

Disable

Slot6 BandWidth Splitting

Splits the bandwidth of slot 3 on riser card 2. The options are as follows:

  • Disable: Do not split.
  • X2: Split by X2.
  • X4: Split by X4.
  • X8: Split by X8.
NOTE:

Only the BIOSs on the following servers support this parameter:

  • BIOS V198 or later on TaiShan 200 servers (models 2280 and 2280K) equipped with Kunpeng 920 7260, 5250, or 5230 processors
  • BIOS V198 or later on TaiShan 200 servers (models 2280, 2280K, 5280, 5280K, and 2280_DEF) equipped with Kunpeng 920 5220 or 3210 processors

Disable

Support Bus Resource Adjustment

Dynamically adjusts the number of PCIe buses for CPU 1. The options are as follows:

  • Enabled
  • Disbled
NOTE:

Only the BIOSs on the following servers support this parameter:

  • TaiShan 200 servers: model 2280 (1620/1620S) and model 5280 (1620/1620S)
  • TaiShan 200K servers: model 2280K (1620/1620S) and model 5280K (1620/1620S)

Enabled

Figure 4-22 shows the CPU 0 PCIe Configuration screen. Table 4-15 describes displayed parameters.

The screen varies according to the PCIe configuration.

Figure 4-22 CPU 0 PCIe Configuration screen
Table 4-15 Parameters on the CPU 0 PCIe Configuration screen

Parameter

Description

CPU 0 PCIe - Port 0

Sets the PCIe parameters of the PCIe port 0 on CPU 0.

CPU 0 PCIe - Port 4

Sets the PCIe parameters of the PCIe port 4 on CPU 0.

CPU 0 PCIe - Port 8

Sets the PCIe parameters of the PCIe port 8 on CPU 0.

CPU 0 PCIe - Port 12

Sets the PCIe parameters of the PCIe port 12 on CPU 0.

CPU 0 PCIe - Port 16

Sets the PCIe parameters of the PCIe port 16 on CPU 0.

CPU 0 PCIe - Port 17

Sets the PCIe parameters of the PCIe port 17 on CPU 0.

NOTE:

If the PCIe port is disabled, the KVM cannot work properly. You are advised to enable the PCIe port.

CPU 0 PCIe - Port 18

Sets the PCIe parameters of the PCIe port 18 on CPU 0.

The following uses CPU 0 PCIe - Port 0 as an example to describe the parameters that need to be set for enabling the PCIe port. Figure 4-23 shows the CPU 0 PCIe - Port 0 screen. Table 4-16 describes the parameters.

Figure 4-23 CPU 0 PCIe - Port 0 screen
Table 4-16 Parameters on the CPU 0 PCIe - Port 0 screen

Parameter

Description

Default Value

PCI-E Port

Sets whether to enable the PCIe port. The options are as follows:

  • Enable: enables the PCIe port.
  • Disable: disables the PCIe port and hides the CFG capacity of the port.

Enable

Link Speed

Sets the link speed. The options are as follows:

  • Gen 1 (2.5 GT/s)
  • Gen 2 (5 GT/s)
  • Gen 3 (8 GT/s)
  • Gen 4 (16 GT/s)

Gen 4 (16 GT/s)

PCI-E Port DeEmphasis

Specifies the de-emphasis settings of the PCIe port. The options are as follows:

  • -6.0 dB
  • -3.5 dB
NOTE:

This parameter is available only when Link Speed is set to Gen 2 (5 GT/s).

-6.0 dB

NOTE:

For TaiShan 200 servers (model 2280, VE), the default value of this parameter is -3.5 dB. This parameter does not take effect when it is set to -6.0 dB.

PCI-E Port Link Status

Indicates the PCIe port link status.

N/A

PCI-E Port Link Max

Indicates the maximum bandwidth of the PCIe port link.

N/A

PCI-E Port Link Speed

Indicates the PCIe port link speed.

NOTE:

This parameter is available when a PCIe device is connected.

N/A

Max Payload Size

Sets the maximum payload size for a PCIe port. The options are as follows:

  • 128B
  • 256B
  • 512B

256B

Figure 4-24 shows the PCIe Slot PXE Control screen. Table 4-17 describes the parameters.

  • The screen varies according to the PCIe configuration.
  • The PCIe Slot1 PXE Control to PCIe Slot8 PXE Control options are available only when External Network Card Boot is set to Enable.
    • This parameter is supported only by BIOS V182 and later on TaiShan 200 servers (models 2280 and 5280).
Figure 4-24 PCIe Slot PXE Control screen
Table 4-17 Parameters on the PCIe Slot PXE Control screen

Parameter

Description

Default Value

PCIe Slot1 PXE Control

Indicates whether to enable PXE for PCIe slot 1. The options are as follows:

  • Enable: enables the PXE port.
  • Disable: disables the PXE port.

Enable

PCIe Slot2 PXE Control

Indicates whether to enable PXE for PCIe slot 2. The options are as follows:

  • Enable: enables the PXE port.
  • Disable: disables the PXE port.

Enable

PCIe Slot3 PXE Control

Indicates whether to enable PXE for PCIe slot 3. The options are as follows:

  • Enable: enables the PXE port.
  • Disable: disables the PXE port.

Enable

PCIe Slot4 PXE Control

Indicates whether to enable PXE for PCIe slot 4. The options are as follows:

  • Enable: enables the PXE port.
  • Disable: disables the PXE port.

Enable

PCIe Slot5 PXE Control

Indicates whether to enable PXE for PCIe slot 5. The options are as follows:

  • Enable: enables the PXE port.
  • Disable: disables the PXE port.

Enable

PCIe Slot6 PXE Control

Indicates whether to enable PXE for PCIe slot 6. The options are as follows:

  • Enable: enables the PXE port.
  • Disable: disables the PXE port.

Enable

PCIe Slot7 PXE Control

Indicates whether to enable PXE for PCIe slot 7. The options are as follows:

  • Enable: enables the PXE port.
  • Disable: disables the PXE port.

Enable

PCIe Slot8 PXE Control

Indicates whether to enable PXE for PCIe slot 8. The options are as follows:

  • Enable: enables the PXE port.
  • Disable: disables the PXE port.

Enable
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Updated: 2023-03-22

Document ID: EDOC1100088647

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